Tenstorrent

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

Machine Learning Engineer at Tenstorrent optimizing LLMs and vision models on custom AI accelerators. Focus on porting, tuning, and validating models end-to-end, working across compiler, kernel, and hardware teams.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

Software engineer at Tenstorrent developing performance-critical GPU-style kernels for AI hardware. Focus on matrix multiplication, attention primitives, and data-movement optimization using C++ and low-level systems programming.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Physical Design Engineer at Tenstorrent architecting AI/ML-driven solutions for RTL-to-GDS flows on advanced semiconductor nodes. Focus on PPA optimization, EDA tool integration, and deploying machine learning techniques in production CAD environments.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Software Engineer leading compiler development at Tenstorrent on TT-Forge, an MLIR-based compiler for AI workloads. Focus on graph transformations, lowering passes, kernel optimizations, and team mentorship across hardware and ML integration.

AI Performance Simulation Architect at Tenstorrent building cycle-accurate performance models for AI accelerators and system-level optimization. Role spans hardware simulation, performance modeling, and architectural design guidance.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for custom AI silicon. Focus on implementing ML operators, optimizing model performance, and integrating real-world models into production.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

Developer Relations Engineer at Tenstorrent building tools, demos, and developer experiences for AI hardware and software platforms. Role spans SDKs, CLIs, dashboards, and educational content to help developers navigate Tenstorrent's RISC-V systems.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

RISC-V Architect at Tenstorrent designing custom CPU cores optimized for AI workloads. Analyze performance requirements, architect microarchitecture, and co-design with compiler and software teams on a unified hardware-software stack.

Package Design Engineer at Tenstorrent designing organic and advanced 2.5D/3D chiplet packaging. Focus on placement, routing, SIPI-aware methodologies, and cross-functional collaboration with suppliers and layout teams.

Software engineer at Tenstorrent developing and optimizing ML models on proprietary RISC-V hardware. Requires strong C++ and Python fundamentals with high interest in machine learning and AI.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Senior backend engineer at Tenstorrent building inference server software for AI workloads on custom silicon. Focus on API design, deployment optimization, and scaling ML inference performance.

Physical Design Engineer at Tenstorrent leading timing and PPA optimization for AI accelerator chips. Responsibilities include synthesis, place-and-route, timing closure, and power optimization on advanced process nodes.

Power Architect at Tenstorrent designing power-aware AI compute systems. Drives architectural strategy for power optimization across high-performance RISC-V CPU and chiplet-based platforms, from pre-silicon modeling through silicon validation.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Software engineer at Tenstorrent building TT-Fabric, a low-level networking layer for distributed AI compute clusters. Focus on protocol design, performance optimization, and synchronization across thousands of processors.

Sr. RTL Design Engineer at Tenstorrent implementing parameterized RTL designs for AI hardware. Focus on microarchitecture optimization, synthesis, timing, and power analysis for high-performance AI accelerators.

Staff physical design engineer at Tenstorrent implementing high-performance CPU and AI/ML accelerator blocks. Owns synthesis-to-tapeout flow, optimizing performance, power, and area on advanced process nodes.

Staff Software Engineer at Tenstorrent building cloud infrastructure, SRE, and operational systems for an AI hardware platform. Focus on infrastructure automation, CI/CD, observability, and bare-metal/Kubernetes provisioning.

ASIC networking engineer at Tenstorrent designing next-generation CPU networking architecture for datacenter and robotics/automotive AI applications. Focus on Ethernet, die-to-die interfaces, NoC design, and RTL implementation.

Automotive and Robotics SoC Architect at Tenstorrent designing scalable system architectures for next-generation automotive AI applications. Requires deep expertise in SoC design, automotive safety standards, and hardware/software co-design.

Power Architect at Tenstorrent designing power management and optimization for AI data center chiplets based on RISC-V. Focus on power delivery networks, thermal analysis, and energy efficiency across silicon and systems.

Senior Design Verification Engineer at Tenstorrent building verification infrastructure for AI compute cores and RISC-V CPUs. Develops SystemVerilog testbenches, coverage-driven tests, and CI/CD pipelines for hardware validation.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Director leading RISC-V software ecosystem growth at Tenstorrent, an AI chip company. Manage engineering teams building system software for embedded, real-time, and server platforms. Collaborate with open-source communities on next-generation RISC-V systems.

Formal Verification Engineer at Tenstorrent applying formal methods to verify high-performance RISC-V CPUs and chiplets. Role involves developing verification strategies, mentoring engineers, and collaborating across design teams to ensure functional correctness and quality standards.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.

Sr. Staff Engineer at Tenstorrent designing system software for AI-optimized automotive SoCs. Role bridges hardware-software interfaces, translates market requirements into technical specs, and collaborates across hardware, product, and software teams.

Static Timing Analysis (STA) methodology engineer at Tenstorrent building timing flows for high-performance AI chip designs. Leads cross-functional STA methodology development, PrimeTime expertise, and ML-assisted timing automation across advanced-node designs.

Sr Staff Engineer at Tenstorrent designing RTL and SoC architectures for AI chips. Focus on microarchitecture, Verilog/VHDL implementation, and performance optimization for compute and memory systems.

CPU Design Verification Technical Lead at Tenstorrent leading a team to validate high-performance RISC-V CPU designs. Responsibilities include test plan development, verification environment design, and collaboration with architecture and microarchitecture teams.

Design Verification Engineer at Tenstorrent leading verification strategy for RISC-V CPU and AI accelerator designs. Owns test environments, mentors engineers, and ensures digital designs meet functionality and performance standards using SystemVerilog and UVM.

Emulation Engineer at Tenstorrent building scalable emulation platforms for AI/ML chiplet-based systems. Focus on DV infrastructure, testbenches, and silicon validation across hardware and software layers.

Infrastructure and Platform Engineer at Tenstorrent building Kubernetes-based platforms for workload orchestration on custom AI accelerator hardware. Focus on platform services, APIs, cluster lifecycle management, and supporting large-scale internal and customer environments.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

Silicon Power & Characterization Engineer at Tenstorrent building post-silicon power analysis for AI SoCs. Conduct power measurements on silicon, correlate against pre-silicon models, and support power architecture improvements across design teams.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Staff Technical Program Manager at Tenstorrent managing end-to-end delivery of AI model IP and software stack to customer environments. Bridges compiler, hardware, and runtime teams to ensure performance, correctness, and deployability of AI systems on custom accelerators.

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Senior Chiplet Physical Design Engineer at Tenstorrent designing and integrating multiple chiplets into System-in-Package solutions. Focus on synthesis, place-and-route, timing closure, and power optimization for advanced CPU and AI silicon at 3nm and below process nodes.

CPU Architect at Tenstorrent designing and optimizing the load-store unit for high-performance RISC-V processors. Focus on micro-architecture, performance modeling, and memory subsystem optimization.

Fellow in High-Speed IO Design at Tenstorrent, a semiconductor AI company. Establish technical vision for die-to-die chiplet PHY IP and analog/mixed-signal design in advanced FinFET processes, mentor engineering teams, and drive strategic company-level outcomes.

RTL engineer at Tenstorrent designing hardware modules for automotive SoC chiplets. Focus on translating system requirements into clean, testable RTL for safety-critical automotive systems.

Senior DFT Engineer at Tenstorrent designing and integrating chiplets for AI systems. Responsible for chip-level DFT strategies, scan chain insertion, memory BIST, and JTAG implementation using industry-standard EDA tools.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

Sr Staff Engineer at Tenstorrent developing ASIC design methodologies and infrastructure for RTL development, verification, and physical implementation. Focus on design quality, automation, and enabling scalability across AI SoC flows.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area in collaboration with validation and physical design teams.

Staff Design for Test Engineer at Tenstorrent building DFT infrastructure for high-performance AI/ML chip architectures. Responsibilities include RTL implementation, ATPG, test coverage analysis, and MBIST across multiple IPs from design through tapeout.

Staff Engineer leading emulation infrastructure and technical strategy for Tenstorrent's high-performance RISC-V CPUs. Focus on CPU verification, debug workflows, and cross-functional collaboration to enable silicon bring-up and customer systems.

Staff Physical Design Engineer at Tenstorrent leading EM and IR-drop simulations for high-performance AI chips. Focus on power delivery, signal integrity, and reliability at advanced nodes (7nm and below).

Field Application Engineer at Tenstorrent supporting enterprise AI deployments across EMEA. Combines systems engineering expertise in hardware/software/firmware with customer-facing technical leadership for Galaxy server deployments and optimization.

Senior software engineer at Tenstorrent building observability and telemetry infrastructure for AI compute clusters. Focus on C++-based metrics collection, distributed systems design, and platform architecture for large-scale AI hardware.

Engineering Program Manager at Tenstorrent leading RISC-V CPU development from specification through tapeout and post-silicon debug. Manages cross-functional teams across architecture, design, verification, and physical design to deliver high-performance silicon.

PCIe validation engineer at Tenstorrent validating high-speed interfaces and debugging hardware-firmware interactions for next-gen AI accelerators. Hands-on lab work with oscilloscopes, protocol analyzers, and JTAG across multi-die chiplet systems.

Senior High Speed Interconnect / Signal Integrity Engineer at Tenstorrent designing and validating high-bandwidth links for large-scale AI systems. Focus on copper and optical interconnect solutions for AI inference and training clusters at speeds up to 1.6T.

Mixed-signal IC layout design engineer at Tenstorrent building high-performance analog IP for advanced FinFET nodes. Translate schematics into manufacturable layouts for PLLs, VCOs, ADCs, and high-speed I/O blocks integrated into SoCs.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Silicon Validation Engineer at Tenstorrent developing test and validation for high-speed chiplet PHY designs. Requires 10+ years of hands-on silicon test experience with oscilloscopes, BERTS, and test automation in Python/Perl/LabVIEW.

Senior engineer at Tenstorrent building performance infrastructure for a RISC-V CPU design. Focus on performance analysis, verification tools, and optimization across pre-silicon and post-silicon phases.

Sr. Staff Engineer at Tenstorrent leading post-silicon validation and bring-up of RISC-V-based SoCs. Owns silicon debug, bare-metal testing, and firmware/software integration across CPU cores, memory systems, and high-speed interfaces.

Staff Analog/Mixed-Signal Design Engineer at Tenstorrent developing die-to-die chiplet PHY IP and PLLs in advanced FinFET processes. Hands-on ownership of design, verification, layout, tape-out, and silicon bring-up for high-performance AI computing platforms.

Staff Design Verification Engineer at Tenstorrent building UVM verification environments for high-performance RISC-V CPU cache and coherence units. Focus on RTL verification, coverage analysis, and complex corner-case validation.

Staff Design for Test Engineer at Tenstorrent implementing DFT features into RTL for high-performance AI/ML chip architectures. Responsibilities include ATPG, scan compression, MBIST, and silicon bring-up support across ASIC design flows.

Staff Design for Test STA Engineer at Tenstorrent building DFT methodology and timing sign-off for next-generation AI processors. Owns static timing analysis, scan insertion, and test mode constraints across complex multi-core SoCs.

Staff Ethernet Validation Engineer at Tenstorrent building validation infrastructure for high-speed networking IP in AI acceleration hardware. Focus on silicon bring-up, SerDes tuning, and Ethernet MAC/PHY testing across simulation to production.

Staff Product Development Engineer at Tenstorrent developing production test programs for AI/ML silicon on ATE platforms. Responsible for translating ATPG patterns into optimized test content, implementing SSN architectures, and supporting silicon bring-up across chiplet and multi-die devices.

Verification Engineer at Tenstorrent verifying digital IP and SoC logic at chiplet integration level. Build verification infrastructure, testbenches, and test plans for a high-performance RISC-V CPU platform. Requires 10+ years verification experience and advanced degree in EE/CS.

Site Reliability Engineer at Tenstorrent building and operating large-scale AI infrastructure. Focus on reliability, observability, and automation across internal clusters and customer deployments in distributed environments.

Infrastructure Automation Engineer at Tenstorrent building automation frameworks for large-scale AI infrastructure provisioning and deployment. Focus on Ansible/AWX, Python/Bash scripting, and CI/CD integration across on-prem data centers and accelerator clusters.