Tenstorrent

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

Machine Learning Engineer at Tenstorrent optimizing LLMs and vision models on custom AI accelerators. Focus on porting, tuning, and validating models end-to-end, working across compiler, kernel, and hardware teams.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

Software engineer at Tenstorrent developing performance-critical GPU-style kernels for AI hardware. Focus on matrix multiplication, attention primitives, and data-movement optimization using C++ and low-level systems programming.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Software Engineer at Tenstorrent bringing up and optimizing AI models on custom accelerator hardware. Work spans model porting, validation, performance tuning, and cross-stack debugging with hardware and compiler teams.

Physical Design Engineer at Tenstorrent architecting AI/ML-driven solutions for RTL-to-GDS flows on advanced semiconductor nodes. Focus on PPA optimization, EDA tool integration, and deploying machine learning techniques in production CAD environments.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Software Engineer leading compiler development at Tenstorrent on TT-Forge, an MLIR-based compiler for AI workloads. Focus on graph transformations, lowering passes, kernel optimizations, and team mentorship across hardware and ML integration.

Design Verification Lead at Tenstorrent guiding a team to validate AI hardware functionality and performance. Focus on mixed-precision data types, on-chip networks, and high-performance compute architectures.

Interconnect and Compute Architect at Tenstorrent designing next-generation CPU networking architecture for AI/ML datacenters and robotics/automotive applications. Focus on Ethernet, die-to-die interfaces, and high-performance computing topologies.

AI Performance Simulation Architect at Tenstorrent building cycle-accurate performance models for AI accelerators and system-level optimization. Role spans hardware simulation, performance modeling, and architectural design guidance.

Director of Customer Engineering at Tenstorrent leading technical relationships with strategic customers for custom AI silicon. Owns conversion of customer requirements into hardware and software specifications, coordinating RTL changes and NEO customization across teams.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for custom AI silicon. Focus on implementing ML operators, optimizing model performance, and integrating real-world models into production.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

CPU Core Design Verification Testbench Lead at Tenstorrent. Own hands-on testbench development and verification for high-performance out-of-order RISC-V CPU cores, spanning CVM methodology, UVM, and AI-assisted debug workflows.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

RISC-V Architect at Tenstorrent designing custom CPU cores optimized for AI workloads. Analyze performance requirements, architect microarchitecture, and co-design with compiler and software teams on a unified hardware-software stack.

Senior Design Verification Engineer at Tenstorrent responsible for end-to-end verification of IOMMU IP in AI/ML systems. Focus on SystemVerilog/UVM, constrained-random verification, coverage closure, and cross-functional collaboration on RISC-V CPU and memory-management designs.

Senior verification engineer at Tenstorrent validating system-level behavior of AI silicon across distributed compute platforms. Focus on end-to-end workload performance, connectivity, and observability for RISC-V-based AI hardware.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Senior backend engineer at Tenstorrent building inference server software for AI workloads on custom silicon. Focus on API design, deployment optimization, and scaling ML inference performance.

Staff RTL engineer at Tenstorrent designing microarchitecture and RTL for AI/ML accelerators and RISC-V CPUs. Work spans pre-silicon design, debug, test, and silicon bring-up across complex digital subsystems and SoC integration.

Staff Physical Design Engineer at Tenstorrent implementing high-performance AI accelerator and CPU blocks from synthesis to tapeout. Focus on PPA optimization, timing closure, and advanced node design on cutting-edge process nodes.

Staff digital design engineer at Tenstorrent building high-performance chiplet-based SoC architectures. Focus on RTL implementation, microarchitecture optimization, and power/performance/area tradeoffs for AI accelerators.

Power Architect at Tenstorrent designing power-aware AI compute systems. Drives architectural strategy for power optimization across high-performance RISC-V CPU and chiplet-based platforms, from pre-silicon modeling through silicon validation.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Software engineer at Tenstorrent building TT-Fabric, a low-level networking layer for distributed AI compute clusters. Focus on protocol design, performance optimization, and synchronization across thousands of processors.

Staff physical design engineer at Tenstorrent implementing high-performance CPU and AI/ML accelerator blocks. Owns synthesis-to-tapeout flow, optimizing performance, power, and area on advanced process nodes.

India Site Lead and System IP Leader at Tenstorrent, a semiconductor/AI company. Oversee technical roadmap for System IP (SoC architecture, interconnects, memory subsystems) while managing the India engineering center's operations, talent, and strategic growth.

Senior physical design engineer at Tenstorrent driving top-level implementation of AI and CPU system-on-chip designs. Focus on floorplanning, power grids, clock networks, and full-chip design closure for next-generation AI hardware.

Sr. Staff Engineer at Tenstorrent designing user-mode drivers and hardware-software interfaces for AI accelerators. Focus on high-performance APIs, kernel integration, and third-party hardware support.

Automotive and Robotics SoC Architect at Tenstorrent designing scalable system architectures for next-generation automotive AI applications. Requires deep expertise in SoC design, automotive safety standards, and hardware/software co-design.

Senior Design Verification Engineer at Tenstorrent building verification infrastructure for AI compute cores and RISC-V CPUs. Develops SystemVerilog testbenches, coverage-driven tests, and CI/CD pipelines for hardware validation.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Senior Staff Engineer at Tenstorrent leading AI workload porting to RISC-V architecture. Focus on DevOps, system software optimization, and cross-functional coordination between IT and hardware teams.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.

Static Timing Analysis (STA) methodology engineer at Tenstorrent building timing flows for high-performance AI chip designs. Leads cross-functional STA methodology development, PrimeTime expertise, and ML-assisted timing automation across advanced-node designs.

Sr Staff Engineer at Tenstorrent designing RTL and SoC architectures for AI chips. Focus on microarchitecture, Verilog/VHDL implementation, and performance optimization for compute and memory systems.

Physical Design Flow Engineer at Tenstorrent developing RTL-to-GDS methodologies and EDA tool optimization for high-performance AI silicon. Focus on power, performance, and area improvements across advanced technology nodes.

Staff Technical Program Manager at Tenstorrent leading cross-functional AI software performance programs on custom hardware. Drive model integration, performance optimization, and roadmap priorities across engineering teams.

Debug Architect at Tenstorrent designing debug and trace capabilities for CPU and AI silicon. Responsible for hardware debug architecture, silicon bring-up, post-silicon validation, and cross-team collaboration on performance analysis infrastructure.

Staff Field Application Engineer at Tenstorrent, a custom AI silicon company. Work directly with enterprise customers to solve AI/ML technical challenges, provide product feedback, and drive adoption of Tenstorrent's hardware and software platform.

Senior embedded engineer at Tenstorrent designing high-performance drivers for AI accelerator hardware. Focus on kernel-level driver architecture, hardware-software interfaces, and customer integration for AI IP platforms.

Senior engineer at Tenstorrent building and optimizing software stacks for AI and RISC-V hardware IP. Focus on firmware, drivers, SDKs, and customer integration across diverse architectures.

Staff Infrastructure Engineer at Tenstorrent designing and operating Kubernetes-native applications for large-scale AI workloads. Focus on inference, training, and CI/CD platform services with Go or Python.

Staff Technical Program Manager at Tenstorrent leading physical design execution for AI/ML and CPU processor projects. Manages cross-functional teams, complex schedules across chiplets, and partnerships with external design services partners.

Sr. Staff Design Verification Engineer at Tenstorrent leading verification strategy for RISC-V CPU and AI accelerator designs. Owns test environments, mentors engineers, and ensures digital designs meet functionality and performance standards.

Emulation Engineer at Tenstorrent building scalable emulation platforms for AI/ML chiplet-based systems. Focus on DV infrastructure, testbenches, and silicon validation across hardware and software layers.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Staff Technical Program Manager at Tenstorrent managing end-to-end delivery of AI model IP and software stack to customer environments. Bridges compiler, hardware, and runtime teams to ensure performance, correctness, and deployability of AI systems on custom accelerators.

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Staff engineer at Tenstorrent leading CPU architectural verification for high-performance RISC-V cores. Develops verification strategies, checkers, and test infrastructure across simulation, emulation, and post-silicon environments.

System IP RTL Design Lead at Tenstorrent, a semiconductor company building AI accelerators. Lead technical definition and integration of complex SoC IPs including memory controllers, interconnects, and peripherals for next-generation datacenter products.

Senior RTL implementation engineer at Tenstorrent designing high-performance RISC-V CPU cores. Focus on synthesis, place-and-route, and PPA optimization across multiple process technologies.

Senior Chiplet Physical Design Engineer at Tenstorrent designing and integrating multiple chiplets into System-in-Package solutions. Focus on synthesis, place-and-route, timing closure, and power optimization for advanced CPU and AI silicon at 3nm and below process nodes.

SoC Chiplet Design Lead at Tenstorrent driving System-on-Chip architecture design for AI and HPC markets. Lead cross-functional teams through RTL, verification, and tape-out with expertise in advanced process nodes and digital design.

Physical Design Engineer at Tenstorrent implementing high-performance partitions for an AI SoC. Owns synthesis, place-and-route, and signoff flows using Synopsys tools on complex semiconductor designs.

Physical Design Engineer at Tenstorrent implementing high-performance CPU and AI/ML accelerator blocks. Owns synthesis-to-tapeout flow, optimizing performance, power, and area on advanced process nodes.

Senior physical design engineer at Tenstorrent leading chiplet and chip-top implementation for high-performance CPU-based SoCs in advanced nodes (5nm and below). Responsibilities include floorplanning, place-and-route, physical verification, and mentoring junior engineers on a multi-chiplet system-in-package project.

CPU Architect at Tenstorrent designing and optimizing the load-store unit for high-performance RISC-V processors. Focus on micro-architecture, performance modeling, and memory subsystem optimization.

Senior DFT Engineer at Tenstorrent designing and integrating chiplets for AI systems. Responsible for chip-level DFT strategies, scan chain insertion, memory BIST, and JTAG implementation using industry-standard EDA tools.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area in collaboration with validation and physical design teams.

Staff Engineer leading emulation infrastructure and technical strategy for Tenstorrent's high-performance RISC-V CPUs. Focus on CPU verification, debug workflows, and cross-functional collaboration to enable silicon bring-up and customer systems.

Physical Design Engineer at Tenstorrent leading Die-to-Die interface implementation from RTL to GDSII for multi-die chiplet architectures. Requires 5+ years at advanced nodes with expertise in high-speed interfaces, timing closure, and full physical design flow.

Senior engineer at Tenstorrent developing low-level Ethernet firmware for AI accelerator hardware. Focus on MAC/PHY/SerDes control, silicon bring-up, and link-training optimization for high-performance networking infrastructure.

Staff Engineer at Tenstorrent responsible for CPU core-level verification of high-performance RISC-V CPUs. Develops UVM-based stimulus, functional models, and coverage for ISA and microarchitectural features; debugs simulation and emulation regressions.

System Management Tools Engineer at Tenstorrent building system management tools (tt-smi), OpenBMC firmware, and hardware-facing functionality for AI accelerator systems. Work spans firmware, drivers, and host software at the hardware/software boundary.

Staff Firmware Engineer at Tenstorrent developing system management firmware for AI accelerator boards. Focus on embedded controllers, bootloaders, Linux drivers, and hardware-software integration in a hybrid Toronto role.

Advanced Packaging Process Engineer at Tenstorrent designing 2.5D/3D chiplet packaging for AI/ML semiconductors. Owns package technology implementation, manages foundry/OSAT partnerships, and drives reliability and manufacturability for high-performance products.

Full-chip physical design verification engineer at Tenstorrent leading silicon signoff and manufacturability closure. Drives DRC, LVS, ERC verification across advanced nodes (7nm-3nm) and collaborates with RTL, PD, and foundry teams on RISC-V CPU tapeouts.

PDK/CAD engineer at Tenstorrent building design infrastructure for AI silicon. Installs and optimizes EDA tools, manages PDKs, and supports physical verification flows for analog, digital, and mixed-signal design.

Power Design Engineer at Tenstorrent leading power analysis and optimization for a 2nm CPU chiplet. Responsibilities include RTL/netlist power analysis using Joules and PrimePower, power vector planning, and collaboration with RTL, synthesis, and physical design teams.

Engineering Program Manager at Tenstorrent leading RISC-V CPU development from specification through tapeout and post-silicon debug. Manages cross-functional teams across architecture, design, verification, and physical design to deliver high-performance silicon.

PCIe validation engineer at Tenstorrent validating high-speed interfaces and debugging hardware-firmware interactions for next-gen AI accelerators. Hands-on lab work with oscilloscopes, protocol analyzers, and JTAG across multi-die chiplet systems.

Senior High Speed Interconnect / Signal Integrity Engineer at Tenstorrent designing and validating high-bandwidth links for large-scale AI systems. Focus on copper and optical interconnect solutions for AI inference and training clusters at speeds up to 1.6T.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Senior engineer at Tenstorrent building performance infrastructure for a RISC-V CPU design. Focus on performance analysis, verification tools, and optimization across pre-silicon and post-silicon phases.

Staff Design Verification Engineer at Tenstorrent building UVM verification environments for high-performance RISC-V CPU cache and coherence units. Focus on RTL verification, coverage analysis, and complex corner-case validation.

Staff Design for Test Engineer at Tenstorrent implementing DFT features into RTL for high-performance AI/ML chip architectures. Responsibilities include ATPG, scan compression, MBIST, and silicon bring-up support across ASIC design flows.

Verification Engineer at Tenstorrent verifying digital IP and SoC logic at chiplet integration level. Build verification infrastructure, testbenches, and test plans for a high-performance RISC-V CPU platform. Requires 10+ years verification experience and advanced degree in EE/CS.

Site Reliability Engineer at Tenstorrent building and operating large-scale AI infrastructure. Focus on reliability, observability, and automation across internal clusters and customer deployments in distributed environments.

Infrastructure engineer at Tenstorrent supporting Linux systems for EDA and silicon design workflows. Responsibilities include maintaining schedulers (LSF, SLURM), managing tool environments, and monitoring system health for shared production environments.

Field Applications Engineer at Tenstorrent selling RISC-V CPU and AI accelerator IP to semiconductor customers. Manages technical engagements, conducts architecture deep-dives, and influences product roadmap through customer feedback.

Munich Site Manager at Tenstorrent leading program planning and execution for silicon and platform initiatives. Bridges Germany-based engineering with global priorities, manages cross-functional teams, and grows the Munich innovation hub.

Software Architect at Tenstorrent leading software stack definition for automotive ADAS, infotainment, and robotics on RISC-V heterogeneous edge computing platforms. Coordinate multi-team efforts across customers and partners to enable next-generation open compute architectures.

Staff engineer at Tenstorrent building release and packaging infrastructure for RISC-V CPU and system IP products. Combines Linux, open-source software, and proprietary tools to enable customer adoption. Focus on CI/CD automation, build systems, and software delivery.

Support Engineer for AI server systems at Tenstorrent in Tokyo. Maintains GPU clusters, storage, and networking infrastructure; handles hardware troubleshooting, on-site repairs, and preventive maintenance for high-performance AI computing environments.

CPU Verification Fellow at Tenstorrent leading verification strategy for next-generation RISC-V high-performance superscalar processors. Requires deep expertise in CPU verification, microarchitecture, SystemVerilog/UVM, and ability to guide large engineering teams from design through tapeout and post-silicon validation.

Senior RTL design engineer at Tenstorrent building high-performance RISC-V CPUs. Focus on microarchitecture, Verilog/VHDL coding, and collaborating with validation and physical design teams on timing and power convergence.

SOC Architect at Tenstorrent designing chiplets for automotive and robotics applications. Translates high-level requirements into detailed architecture, balancing performance, power, and functional safety constraints.

CPU Core Design Verification Test Generator Lead at Tenstorrent. Lead development of test generators for high-performance out-of-order RISC-V cores, own verification strategy and methodology, and guide a small team of engineers on ISA and microarchitectural validation.

DFT Engineer at Tenstorrent designing test and design-for-manufacturability strategies for multi-chiplet automotive SoCs. Bridges silicon design, DFT, and manufacturing partners to meet performance, quality, and safety targets.

SoC Physical Design Verification Engineer at Tenstorrent leading full-chip signoff and physical verification closure (DRC, LVS, ERC) for advanced-node silicon. Requires 7–14 years of CPU/IP/SoC verification experience and expertise with industry tools like Calibre, ICV, and Innovus.

Signal Integrity Engineer at Tenstorrent designing high-speed PCB and package interconnects for AI hardware. Focus on breakout design, SI/PI simulation, and validation at 10Gbps+ speeds.

Sr. Staff Design Verification Engineer at Tenstorrent building verification infrastructure for high-performance RISC-V CPU clusters and SoCs. Focus on SystemVerilog/UVM-based verification, multi-IP integration, and system-level validation.

Staff silicon validation engineer at Tenstorrent developing hardware infrastructure for die-to-die chiplet validation and AI processor IP testchips. Hands-on role performing electrical characterization, high-speed measurements, and customer silicon bring-up using lab equipment and test automation.

Manager, Finance Center of Excellence at Tenstorrent building and leading the Bangalore finance hub from the ground up. Responsibilities include entity accounting, close operations, statutory compliance, team leadership, and expanding the COE to include AI-driven finance automation.

Manager of Supplier Quality at Tenstorrent, a custom silicon AI chip company. Build the supplier quality organization from scratch, managing foundries, substrate vendors, and OSAT partners to ensure reliability and yield standards across the manufacturing ecosystem.

Business Development Lead at Tenstorrent identifying opportunities and managing client relationships for sovereign AI solutions in India. Focus on pipeline development, partnerships with enterprises and government, and go-to-market execution across the region.

Sustaining Test Engineer at Tenstorrent providing on-site support at OSAT partners in Taiwan. Responsible for production test operations, yield improvements, manufacturing issue resolution, and test solution deployment across wafer probe, package test, and system-level test.

Associate in Corporate Development at Tenstorrent, an AI hardware company. Executes M&A, financial modeling, partnerships, and strategic initiatives alongside the C-suite. Hybrid role based in Toronto, Austin, or Santa Clara.

Staff Cost & Inventory Specialist at Tenstorrent, a hardware AI company. Owns product cost forecasting, inventory analytics, and supply chain finance across chips, boards, and systems. Partners with operations to improve margins and production planning.

Global Supply Chain Manager at Tenstorrent managing suppliers and supply chain operations across Asia. Reports to Director of Commodity Management; handles supplier performance, cost reduction, and supply risk mitigation for AI hardware platform.

HR Project Manager at Tenstorrent managing People programs including promotions, performance reviews, and employee surveys. Contractor role focused on operational execution and cross-functional coordination in a fast-moving AI hardware company.

Inventory Manager at Tenstorrent managing end-to-end semiconductor inventory across global locations. Requires 5+ years in semiconductor/electronics manufacturing with SAP S4 HANA expertise and responsibility for 99%+ accuracy in inventory records and material flow optimization.