Remote & hybrid AI jobs

Solutions Architect at LangChain designing and deploying production AI infrastructure and multi-agent systems for enterprise customers. Combines infrastructure engineering, agent development, and customer-facing technical leadership.

Staff Machine Learning Engineer at Twilio building data pipelines, ML infrastructure, and real-time intelligence systems for the Trust Intelligence Platform. Focus on orchestration, feature stores, model training/inference, and cloud-native MLOps.

Applied AI Engineer at Anthropic in Tokyo, advising customers on Claude deployment and LLM implementation patterns. Combines technical architecture guidance, evaluation frameworks, and hands-on engineering support across customer product teams.

Senior Software Engineer at Paradigm building Surface.ai, a talent and culture intelligence platform. Full-stack role shipping AI-driven features across frontend, backend, and data pipelines in a small, fast-moving team.

Machine Learning Engineer at Airbnb building agentic AI systems for customer support. Focus on LLM fine-tuning, multi-agent orchestration, RAG, and production ML infrastructure for Chat and Voice AI assistants.

Senior Solutions Engineer at Webflow, an AI-native digital experience platform. Role involves partnering with customers and sales to architect and demonstrate solutions, conduct discovery and technical validation, and influence product direction. Remote-first in US/Canada with 25% travel.

Engineering Manager, Head of Machine Learning at Hightouch, a marketing AI platform. Lead ML efforts across personalization, identity resolution, content generation, and ML infrastructure for data-driven marketing workflows.

Bluespec design engineer at MatX building silicon for GenAI. Develop hardware RTL using Bluespec (a functional language for hardware), focusing on compute, memory, and connectivity subsystems. Haskell proficiency required; prior hardware experience a bonus.

Verification Engineer at Tenstorrent verifying digital IP and SoC logic at chiplet integration level. Build verification infrastructure, testbenches, and test plans for a high-performance RISC-V CPU platform. Requires 10+ years verification experience and advanced degree in EE/CS.

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Staff Software Engineer at Tenstorrent building cloud infrastructure, SRE, and operational systems for an AI hardware platform. Focus on infrastructure automation, CI/CD, observability, and bare-metal/Kubernetes provisioning.

Staff Technical Program Manager at Tenstorrent managing end-to-end delivery of AI model IP and software stack to customer environments. Bridges compiler, hardware, and runtime teams to ensure performance, correctness, and deployability of AI systems on custom accelerators.

Staff Ethernet Validation Engineer at Tenstorrent building validation infrastructure for high-speed networking IP in AI acceleration hardware. Focus on silicon bring-up, SerDes tuning, and Ethernet MAC/PHY testing across simulation to production.

Staff Physical Design Engineer at Tenstorrent leading EM and IR-drop simulations for high-performance AI chips. Focus on power delivery, signal integrity, and reliability at advanced nodes (7nm and below).

Staff physical design engineer at Tenstorrent implementing high-performance CPU and AI/ML accelerator blocks. Owns synthesis-to-tapeout flow, optimizing performance, power, and area on advanced process nodes.

Staff Engineer leading emulation infrastructure and technical strategy for Tenstorrent's high-performance RISC-V CPUs. Focus on CPU verification, debug workflows, and cross-functional collaboration to enable silicon bring-up and customer systems.

Staff Design for Test STA Engineer at Tenstorrent building DFT methodology and timing sign-off for next-generation AI processors. Owns static timing analysis, scan insertion, and test mode constraints across complex multi-core SoCs.

Staff Analog/Mixed-Signal Design Engineer at Tenstorrent developing die-to-die chiplet PHY IP and PLLs in advanced FinFET processes. Hands-on ownership of design, verification, layout, tape-out, and silicon bring-up for high-performance AI computing platforms.

Sr Staff Engineer at Tenstorrent designing RTL and SoC architectures for AI chips. Focus on microarchitecture, Verilog/VHDL implementation, and performance optimization for compute and memory systems.

Sr. Staff Engineer at Tenstorrent leading post-silicon validation and bring-up of RISC-V-based SoCs. Owns silicon debug, bare-metal testing, and firmware/software integration across CPU cores, memory systems, and high-speed interfaces.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area in collaboration with validation and physical design teams.

Sr. Staff Engineer at Tenstorrent designing system software for AI-optimized automotive SoCs. Role bridges hardware-software interfaces, translates market requirements into technical specs, and collaborates across hardware, product, and software teams.

Sr Staff Engineer at Tenstorrent developing ASIC design methodologies and infrastructure for RTL development, verification, and physical implementation. Focus on design quality, automation, and enabling scalability across AI SoC flows.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Senior engineer at Tenstorrent building performance infrastructure for a RISC-V CPU design. Focus on performance analysis, verification tools, and optimization across pre-silicon and post-silicon phases.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent building TT-Fabric, a low-level networking layer for distributed AI compute clusters. Focus on protocol design, performance optimization, and synchronization across thousands of processors.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Software engineer at Tenstorrent developing and optimizing ML models on proprietary RISC-V hardware. Requires strong C++ and Python fundamentals with high interest in machine learning and AI.

Site Reliability Engineer at Tenstorrent building and operating large-scale AI infrastructure. Focus on reliability, observability, and automation across internal clusters and customer deployments in distributed environments.

Silicon Power & Characterization Engineer at Tenstorrent building post-silicon power analysis for AI SoCs. Conduct power measurements on silicon, correlate against pre-silicon models, and support power architecture improvements across design teams.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

Senior Design Verification Engineer at Tenstorrent building verification infrastructure for AI compute cores and RISC-V CPUs. Develops SystemVerilog testbenches, coverage-driven tests, and CI/CD pipelines for hardware validation.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

RTL engineer at Tenstorrent designing hardware modules for automotive SoC chiplets. Focus on translating system requirements into clean, testable RTL for safety-critical automotive systems.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

Power Architect at Tenstorrent designing power management and optimization for AI data center chiplets based on RISC-V. Focus on power delivery networks, thermal analysis, and energy efficiency across silicon and systems.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Mixed-signal IC layout design engineer at Tenstorrent building high-performance analog IP for advanced FinFET nodes. Translate schematics into manufacturable layouts for PLLs, VCOs, ADCs, and high-speed I/O blocks integrated into SoCs.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

Infrastructure and Platform Engineer at Tenstorrent building Kubernetes-based platforms for workload orchestration on custom AI accelerator hardware. Focus on platform services, APIs, cluster lifecycle management, and supporting large-scale internal and customer environments.

Infrastructure Automation Engineer at Tenstorrent building automation frameworks for large-scale AI infrastructure provisioning and deployment. Focus on Ansible/AWX, Python/Bash scripting, and CI/CD integration across on-prem data centers and accelerator clusters.