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Sr. RTL Design Engineer at Tenstorrent implementing parameterized RTL designs for AI hardware. Focus on microarchitecture optimization, synthesis, timing, and power analysis for high-performance AI accelerators.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent building TT-Fabric, a low-level networking layer for distributed AI compute clusters. Focus on protocol design, performance optimization, and synchronization across thousands of processors.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

Software Engineer leading compiler development at Tenstorrent on TT-Forge, an MLIR-based compiler for AI workloads. Focus on graph transformations, lowering passes, kernel optimizations, and team mentorship across hardware and ML integration.

Software engineer at Tenstorrent developing and optimizing ML models on proprietary RISC-V hardware. Requires strong C++ and Python fundamentals with high interest in machine learning and AI.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Senior Design Verification Engineer at Tenstorrent building verification infrastructure for AI compute cores and RISC-V CPUs. Develops SystemVerilog testbenches, coverage-driven tests, and CI/CD pipelines for hardware validation.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

Power Architect at Tenstorrent designing power management and optimization for AI data center chiplets based on RISC-V. Focus on power delivery networks, thermal analysis, and energy efficiency across silicon and systems.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Formal Verification Engineer at Tenstorrent applying formal methods to verify high-performance RISC-V CPUs and chiplets. Role involves developing verification strategies, mentoring engineers, and collaborating across design teams to ensure functional correctness and quality standards.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

Director leading RISC-V software ecosystem growth at Tenstorrent, an AI chip company. Manage engineering teams building system software for embedded, real-time, and server platforms. Collaborate with open-source communities on next-generation RISC-V systems.