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Senior ML Software Engineer at Cerebras Systems integrating and validating the software stack for the Cerebras AI platform. Focus on distributed systems debugging, automation, and reliability across ML infrastructure and hardware/software co-design.

Product Manager for Strategic Verticals at Cerebras Systems, a wafer-scale AI chip company. Role involves embedding with strategic customers to translate their AI ambitions into production solutions, design performance benchmarks, and shape product roadmap based on customer insights.

Principal ML Investigator at Cerebras Systems building ML research and advanced development on the company's wafer-scale AI chip platform. Focus on post-training, dataset optimization, LLM pretraining, sparsity, and domain-specific agents.

Principal Engineer at Cerebras Systems building reliability infrastructure for the world's fastest AI inference service. Owns SLO definition, incident response, and fault-tolerance mechanisms across distributed wafer-scale systems and multi-region cloud deployments.

Principal Engineer at Cerebras Systems building the cloud platform for wafer-scale AI inference. Owns multi-region architecture, reliability, latency optimization, and production operations for high-QPS inference services.

Performance & Reliability Engineer at Cerebras Systems optimizing ML workloads on the company's wafer-scale AI chip. Focus on characterizing hardware/software performance, power efficiency, and thermal management for next-generation AI systems.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations, implementing parallel algorithms, and leveraging custom hardware architecture.

ML Systems Performance Engineer at Cerebras Systems optimizing inference speed and throughput on wafer-scale AI chips. Role spans kernel optimization, performance modeling, and debugging across hardware and software layers.

Network Architect at Cerebras Systems designing front-end datacenter and interconnect architecture for AI/ML clusters. Responsible for developing proof-of-concept network designs, resolving performance bottlenecks, and leading cross-functional projects integrating hardware and software components.

ML Software Tool Development Engineer at Cerebras Systems building debugging, validation, and observability platforms for the world's largest AI chip. Focus on system-level profiling, compiler instrumentation, and high-performance hardware-software co-design.

Manufacturing Test Manager at Cerebras Systems leading test engineering teams for AI chip production. Oversees test strategies, automation systems, and quality assurance for wafer-scale AI processors.

ML Performance Benchmarking Engineer at Cerebras Systems building observability and benchmarking infrastructure for AI inference on wafer-scale hardware. Focus on telemetry systems, performance analysis, and optimization across the full software stack.

Lead RTL Design Engineer at Cerebras Systems designing the next-generation Wafer Scale Engine AI chip. Responsibilities include RTL development, synthesis, vendor management, and collaboration with design verification and physical design teams to deliver high-performance semiconductor architectures.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and domain-specific language programming.

Infrastructure Hardware Technical Program Manager at Cerebras Systems driving end-to-end delivery of server and network platforms for AI clusters. Manages OEM/ODM partnerships, qualification, and production rollout across multi-team programs.

Inference Frontend engineer at Cerebras Systems building software for the world's largest AI chip. Recent graduate role collaborating on real-world challenges across the software stack, from hardware to ML frameworks.

Engineering Manager, Kernel Reliability at Cerebras Systems. Lead a team improving reliability of advanced compute clusters and inference/training services. Focus on diagnostic tooling, failure analysis, and kernel-level debugging for wafer-scale AI chip systems.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

Early-career compiler engineer at Cerebras Systems building LLVM-based code generation and optimization for the company's wafer-scale AI chip architecture. Focus on low-level compiler components, backend passes, and single-core code generation for massively parallel systems.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Design Verification Engineer at Cerebras Systems building verification infrastructure for the world's largest AI chip. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM across simulation, emulation, and silicon bring-up phases.

Compute Server Platform Architect at Cerebras Systems designing x86 server platforms for AI cluster infrastructure. Owns server architecture, performance modeling, and vendor partnerships for Cerebras' wafer-scale AI accelerator systems.

New graduate engineer at Cerebras Systems working on wafer-scale AI chip architecture, kernel design, and performance modeling. Role spans hardware-software codesign, system bringup, and validation across simulators and actual hardware.

Applied Machine Learning Research Scientist at Cerebras Systems building LLM training, fine-tuning, and post-training pipelines on wafer-scale AI hardware. Focus on implementing ML techniques at scale, debugging ML systems, and optimizing training workflows.

AI Silicon Physical Design Engineer at Cerebras Systems building wafer-scale AI chips. Role focuses on synthesizing, placing, routing high-speed designs, and full-chip physical verification for the world's largest AI processor.