Find your next AI-scored role.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

Electrical engineer at Cerebras Systems designing printed circuit boards for AI inference chips. Lead PCB development from schematic through production, collaborate with cross-functional teams on power delivery and signal integrity.

Early-career compiler engineer at Cerebras Systems building LLVM-based code generation and optimization for the company's wafer-scale AI chip architecture. Focus on low-level compiler components, backend passes, and single-core code generation for massively parallel systems.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Distributed Software Engineer at Cerebras Systems building cluster orchestration and monitoring software for wafer-scale AI supercomputers. Focus on bare-metal automation, Kubernetes-based scheduling, and large-scale distributed systems infrastructure.

Design Validation Test Lead at Cerebras Systems, a hardware AI chip company. Own end-to-end DVT for complex PCBs and systems, including power delivery, high-speed I/O, and thermal validation. Drive debug, root-cause analysis, and design closure.

Design Verification Engineer at Cerebras Systems building verification infrastructure for the world's largest AI chip. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM across simulation, emulation, and silicon bring-up phases.

Compute Server Platform Architect at Cerebras Systems designing x86 server platforms for AI cluster infrastructure. Owns server architecture, performance modeling, and vendor partnerships for Cerebras' wafer-scale AI accelerator systems.

New graduate engineer at Cerebras Systems working on wafer-scale AI chip architecture, kernel design, and performance modeling. Role spans hardware-software codesign, system bringup, and validation across simulators and actual hardware.

Applied Machine Learning Research Scientist at Cerebras Systems building LLM training, fine-tuning, and post-training pipelines on wafer-scale AI hardware. Focus on implementing ML techniques at scale, debugging ML systems, and optimizing training workflows.

AI Silicon Physical Design Engineer at Cerebras Systems building wafer-scale AI chips. Role focuses on synthesizing, placing, routing high-speed designs, and full-chip physical verification for the world's largest AI processor.

Product Manager for AI Models at Cerebras Systems, leading the strategic model portfolio for the world's fastest AI inference platform. Owns model roadmap decisions, quality standards, customer partnerships, and go-to-market launches for frontier and open-source models.

Entry-level AI Infrastructure Operations Engineer at Cerebras Systems supporting deployment, monitoring, and troubleshooting of wafer-scale AI chip infrastructure in data center environments. Focuses on hardware bring-up, telemetry monitoring, and first-line incident response.

AI Infrastructure Operations Engineer at Cerebras Systems managing wafer-scale AI compute clusters. Responsibilities include cluster health monitoring, container deployment, resource optimization, and 24/7 infrastructure support for large-scale ML workloads.

AI/ML Research Scientist at Cerebras Systems designing and developing AI models and training methodologies on wafer-scale hardware. Work spans optimization theory, model architecture, and computational science to explore new algorithmic possibilities enabled by novel hardware architecture.

R&D Engineer at Cerebras Systems designing and optimizing AI/ML and scientific computing workloads on wafer-scale hardware. Work spans algorithm design, compiler co-optimization, and hardware architecture to advance state-of-the-art performance benchmarks.

Advanced Packaging Technologist & Lead at Cerebras Systems designing semiconductor packaging technologies for AI chips. Responsibilities include 2.5D/3D stacking, heterogeneous integration, and high-density interconnect architectures for wafer-scale AI compute platforms.

Compiler engineer at Cerebras Systems building the Tungsten dataflow compiler for wafer-scale AI processors. Design and implement compiler passes, optimize code generation for novel hardware, and co-design language constructs for efficient execution across hundreds of thousands of cores.

Staff Storage Systems Administrator at Crusoe, a vertically integrated AI infrastructure company. Lead architect and operator of the data layer for AI cloud, managing petabyte-scale storage systems, performance optimization, and vendor strategy for Fortune 500 and AI research customers.

Senior Machine Learning Platform Engineer at Coinbase building foundational ML infrastructure for feature engineering, training, and serving models at scale. Focus on distributed systems, low-latency inference, and developer tooling for ML teams.

Staff Engineer at MongoDB building AI-powered code transformation tools that modernize legacy applications into microservices architectures. Lead the Code Gen team in designing and optimizing code transformation workflows leveraging LLMs and GenAI capabilities.

Staff Engineer at MongoDB building AI-powered code transformation tools that modernize legacy applications into microservices architectures. Lead the Code Gen team in designing and optimizing code transformation workflows leveraging LLMs and GenAI capabilities.

Staff Software Engineer at Crusoe building Virtual Pool Service and Capacity Management Intelligence systems for GPU fleet allocation and management. Focus on distributed systems, infrastructure automation, and cloud platform reliability at scale.

Flight Test Operator at Anduril Industries supporting autonomous aircraft development. Operates ground control software, flies fixed-wing and VTOL platforms, and assists with system integration and testing for defense autonomy programs.

Systems Safety Engineer at Anduril Industries supporting design, development, and validation of advanced algorithmic capabilities for AI-powered command and control systems. Role bridges system design, requirements management, modeling/simulation, and verification activities for defense technology.