TL;DR
Digital Design Engineer at Tenstorrent building high-performance chiplet-based SoC architectures. RTL implementation in SystemVerilog, verification support, and collaboration with senior mentors on AI hardware design.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Engineer, SoC RTL Engineer
We are looking for a Digital Design Engineer to help build and optimize high-performance chiplet-based SoC architectures. This role is ideal for passionate junior engineers or recent graduates who want to grow their career at the intersection of microarchitecture, RTL implementation, and performance/power-aware design.
Location: Tokyo, Japan (Hybrid - Flexible working hours and remote work options available)
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Benefits & Work Style at Tokyo Office
- Competitive Salary: We offer a competitive compensation package aligned with industry standards, your baseline skills, and potential.
- Flexible Work Culture: To support a healthy work-life balance, we offer flexible working hours (flextime) and remote work options (hybrid style) based out of our Tokyo office.
Who You Are
- An Aspiring Digital Design Engineer: You have a solid foundational understanding of computer architecture and digital logic design.
- Eager to Learn RTL: You have academic or internship experience in RTL development (SystemVerilog) and are excited to learn the full ASIC flow.
- PPA Conscious: You understand the basic concepts of optimizing for Power, Performance, and Area (PPA).
- Collaborative & Curious: You are a natural team player who thrives on learning from peers, participating in code reviews, and asking questions.
- Problem Solver: You possess strong analytical skills and a desire to tackle complex hardware design challenges.
What You Will Do (What We Need)
- HDL Coding: Utilize hardware description languages (SystemVerilog) to implement and modify custom IP blocks and SoC components under the guidance of senior mentors.
- RTL Implementation: Assist in the design and integration of compute, interconnect, or memory-heavy blocks.
- Verification Support: Contribute to verification and validation efforts using emulation, FPGA prototyping, or basic UVM flows.
- Collaborate Across Teams: Work closely with senior engineers to understand design specifications and support backend synthesis and timing closure teams.
- Bonus Points: Basic understanding of RISC-V Architecture, on-chip fabric/interconnect designs, DFT, or basic hardware debugging experience is preferable but not required.
What You Will Learn
- Advanced Chiplet Design: How cutting-edge chiplet designs are built, from initial spec to silicon.
- Industry-Leading Collaboration: What it takes to collaborate with global teams designing novel processor and memory architectures.
- Cross-Functional Workflows: How design, Design Verification (DV), physical design, and firmware teams come together to deliver world-class AI hardware.
- Mentorship: Receive hands-on guidance and mentorship from industry-leading silicon experts.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.