AI jobs in Santa Clara

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Static Timing Analysis (STA) methodology engineer at Tenstorrent building timing flows for high-performance AI chip designs. Leads cross-functional STA methodology development, PrimeTime expertise, and ML-assisted timing automation across advanced-node designs.

Staff Ethernet Validation Engineer at Tenstorrent building validation infrastructure for high-speed networking IP in AI acceleration hardware. Focus on silicon bring-up, SerDes tuning, and Ethernet MAC/PHY testing across simulation to production.

Staff Design for Test STA Engineer at Tenstorrent building DFT methodology and timing sign-off for next-generation AI processors. Owns static timing analysis, scan insertion, and test mode constraints across complex multi-core SoCs.

Staff Design for Test Engineer at Tenstorrent building DFT infrastructure for high-performance AI/ML chip architectures. Responsibilities include RTL implementation, ATPG, test coverage analysis, and MBIST across multiple IPs from design through tapeout.

Senior software engineer at Tenstorrent building observability and telemetry infrastructure for AI compute clusters. Focus on C++-based metrics collection, distributed systems design, and platform architecture for large-scale AI hardware.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Silicon Validation Engineer at Tenstorrent developing test and validation for high-speed chiplet PHY designs. Requires 10+ years of hands-on silicon test experience with oscilloscopes, BERTS, and test automation in Python/Perl/LabVIEW.

Power Architect at Tenstorrent designing power management and optimization for AI data center chiplets based on RISC-V. Focus on power delivery networks, thermal analysis, and energy efficiency across silicon and systems.

Senior High Speed Interconnect / Signal Integrity Engineer at Tenstorrent designing and validating high-bandwidth links for large-scale AI systems. Focus on copper and optical interconnect solutions for AI inference and training clusters at speeds up to 1.6T.

Infrastructure and Platform Engineer at Tenstorrent building Kubernetes-based platforms for workload orchestration on custom AI accelerator hardware. Focus on platform services, APIs, cluster lifecycle management, and supporting large-scale internal and customer environments.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Formal Verification Engineer at Tenstorrent applying formal methods to verify high-performance RISC-V CPUs and chiplets. Role involves developing verification strategies, mentoring engineers, and collaborating across design teams to ensure functional correctness and quality standards.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

Physical Design Engineer at Tenstorrent architecting AI/ML-driven solutions for RTL-to-GDS flows on advanced semiconductor nodes. Focus on PPA optimization, EDA tool integration, and deploying machine learning techniques in production CAD environments.