AI jobs in Santa Clara

Physical Design Flow Engineer at Tenstorrent developing RTL-to-GDS methodologies and EDA tool optimization for high-performance AI silicon. Focus on power, performance, and area improvements across advanced technology nodes.

Staff Technical Program Manager at Tenstorrent leading physical design execution for AI/ML and CPU processor projects. Manages cross-functional teams, complex schedules across chiplets, and partnerships with external design services partners.

Advanced Packaging Process Engineer at Tenstorrent designing 2.5D/3D chiplet packaging for AI/ML semiconductors. Owns package technology implementation, manages foundry/OSAT partnerships, and drives reliability and manufacturability for high-performance products.

Full-chip physical design verification engineer at Tenstorrent leading silicon signoff and manufacturability closure. Drives DRC, LVS, ERC verification across advanced nodes (7nm-3nm) and collaborates with RTL, PD, and foundry teams on RISC-V CPU tapeouts.

PDK/CAD engineer at Tenstorrent building design infrastructure for AI silicon. Installs and optimizes EDA tools, manages PDKs, and supports physical verification flows for analog, digital, and mixed-signal design.

Senior physical design engineer at Tenstorrent driving top-level implementation of AI and CPU system-on-chip designs. Focus on floorplanning, power grids, clock networks, and full-chip design closure for next-generation AI hardware.

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Static Timing Analysis (STA) methodology engineer at Tenstorrent building timing flows for high-performance AI chip designs. Leads cross-functional STA methodology development, PrimeTime expertise, and ML-assisted timing automation across advanced-node designs.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Senior High Speed Interconnect / Signal Integrity Engineer at Tenstorrent designing and validating high-bandwidth links for large-scale AI systems. Focus on copper and optical interconnect solutions for AI inference and training clusters at speeds up to 1.6T.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

Physical Design Engineer at Tenstorrent architecting AI/ML-driven solutions for RTL-to-GDS flows on advanced semiconductor nodes. Focus on PPA optimization, EDA tool integration, and deploying machine learning techniques in production CAD environments.