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Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Senior engineer at Tenstorrent building performance infrastructure for a RISC-V CPU design. Focus on performance analysis, verification tools, and optimization across pre-silicon and post-silicon phases.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Site Reliability Engineer at Tenstorrent building and operating large-scale AI infrastructure. Focus on reliability, observability, and automation across internal clusters and customer deployments in distributed environments.

Silicon Power & Characterization Engineer at Tenstorrent building post-silicon power analysis for AI SoCs. Conduct power measurements on silicon, correlate against pre-silicon models, and support power architecture improvements across design teams.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

PCIe validation engineer at Tenstorrent validating high-speed interfaces and debugging hardware-firmware interactions for next-gen AI accelerators. Hands-on lab work with oscilloscopes, protocol analyzers, and JTAG across multi-die chiplet systems.

Engineering Program Manager at Tenstorrent leading RISC-V CPU development from specification through tapeout and post-silicon debug. Manages cross-functional teams across architecture, design, verification, and physical design to deliver high-performance silicon.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

Emulation Engineer at Tenstorrent building scalable emulation platforms for AI/ML chiplet-based systems. Focus on DV infrastructure, testbenches, and silicon validation across hardware and software layers.