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GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Field Application Engineer at Tenstorrent supporting enterprise AI deployments across EMEA. Combines systems engineering expertise in hardware/software/firmware with customer-facing technical leadership for Galaxy server deployments and optimization.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

PCIe validation engineer at Tenstorrent validating high-speed interfaces and debugging hardware-firmware interactions for next-gen AI accelerators. Hands-on lab work with oscilloscopes, protocol analyzers, and JTAG across multi-die chiplet systems.

Engineering Program Manager at Tenstorrent leading RISC-V CPU development from specification through tapeout and post-silicon debug. Manages cross-functional teams across architecture, design, verification, and physical design to deliver high-performance silicon.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

Director leading RISC-V software ecosystem growth at Tenstorrent, an AI chip company. Manage engineering teams building system software for embedded, real-time, and server platforms. Collaborate with open-source communities on next-generation RISC-V systems.

Emulation Engineer at Tenstorrent building scalable emulation platforms for AI/ML chiplet-based systems. Focus on DV infrastructure, testbenches, and silicon validation across hardware and software layers.

Developer Relations Engineer at Tenstorrent building tools, demos, and developer experiences for AI hardware and software platforms. Role spans SDKs, CLIs, dashboards, and educational content to help developers navigate Tenstorrent's RISC-V systems.

Design Verification Engineer at Tenstorrent leading verification strategy for RISC-V CPU and AI accelerator designs. Owns test environments, mentors engineers, and ensures digital designs meet functionality and performance standards using SystemVerilog and UVM.

CPU Design Verification Technical Lead at Tenstorrent leading a team to validate high-performance RISC-V CPU designs. Responsibilities include test plan development, verification environment design, and collaboration with architecture and microarchitecture teams.

CPU Architect at Tenstorrent designing and optimizing the load-store unit for high-performance RISC-V processors. Focus on micro-architecture, performance modeling, and memory subsystem optimization.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for custom AI silicon. Focus on implementing ML operators, optimizing model performance, and integrating real-world models into production.

Automotive and Robotics SoC Architect at Tenstorrent designing scalable system architectures for next-generation automotive AI applications. Requires deep expertise in SoC design, automotive safety standards, and hardware/software co-design.

Senior Chiplet Physical Design Engineer at Tenstorrent designing and integrating multiple chiplets into System-in-Package solutions. Focus on synthesis, place-and-route, timing closure, and power optimization for advanced CPU and AI silicon at 3nm and below process nodes.

ASIC networking engineer at Tenstorrent designing next-generation CPU networking architecture for datacenter and robotics/automotive AI applications. Focus on Ethernet, die-to-die interfaces, NoC design, and RTL implementation.

AI Performance Simulation Architect at Tenstorrent building cycle-accurate performance models for AI accelerators and system-level optimization. Role spans hardware simulation, performance modeling, and architectural design guidance.

AI Evaluations Lead at Cresta, responsible for designing and scaling end-to-end quality frameworks for AI agent systems. Role involves architecting LLM evaluation methodologies, leading QA teams, and ensuring reliable AI deployment for enterprise customers.

Senior Product Manager at Datadog owning the Code Security product roadmap for application vulnerability management and software composition analysis. Focus on customer discovery, cross-functional execution, and launching new security capabilities.

Senior Data Engineer at Pinterest's tvScientific division building scalable data infrastructure for CTV advertising. Focus on Spark/Scala pipelines, AWS data lakes, and cross-functional collaboration to support performance marketing optimization.

Staff Data Engineer at Pinterest's tvScientific division, building scalable data infrastructure on AWS using Spark and Scala. Focus on core data pipelines, knowledge graphs, and APIs for a CTV advertising platform.

Staff Data Engineer at Pinterest/tvScientific building identity resolution and data governance platforms. Focus on scalable pipelines, privacy-by-design, and cross-functional collaboration on CTV advertising infrastructure.

Senior Solutions Architect at Databricks leading technical strategy for new data and AI platform engagements in the Nordics. Advises C-level executives on complex data architecture, drives adoption, and mentors junior architects.

Senior Backend Engineer (AI) at GitLab building AI-assisted and agentic CI/CD features. Focus on integrating GitLab's Duo Agent Platform into pipeline execution, designing observability for AI agents, and scaling infrastructure for enterprise CI workloads.