Find your next AI-scored role.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Sr. Engineer at Tenstorrent focused on pre-silicon verification of DFD logic in advanced AI SoCs. Develops verification environments for scan, MBIST, and debug features using UVM and Siemens Tessent workflows.

Senior engineer at Tenstorrent building performance infrastructure for a RISC-V CPU design. Focus on performance analysis, verification tools, and optimization across pre-silicon and post-silicon phases.

Senior kernel engineer at Tenstorrent optimizing performance-critical kernels for AI hardware. Focus on GPU-style kernel design, low-level optimization, and hardware-software co-design using C++ and profiling-driven approaches.

Software engineer at Tenstorrent building distributed systems for AI and HPC clusters. Focus on multi-node coordination, inter-node communication, and scaling inference/training infrastructure using C/C++ and systems programming.

Software engineer at Tenstorrent building TT-Fabric, a low-level networking layer for distributed AI compute clusters. Focus on protocol design, performance optimization, and synchronization across thousands of processors.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Software engineer at Tenstorrent developing and optimizing ML models on proprietary RISC-V hardware. Requires strong C++ and Python fundamentals with high interest in machine learning and AI.

Site Reliability Engineer at Tenstorrent building and operating large-scale AI infrastructure. Focus on reliability, observability, and automation across internal clusters and customer deployments in distributed environments.

Silicon Power & Characterization Engineer at Tenstorrent building post-silicon power analysis for AI SoCs. Conduct power measurements on silicon, correlate against pre-silicon models, and support power architecture improvements across design teams.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

Senior Design Verification Engineer at Tenstorrent building verification infrastructure for AI compute cores and RISC-V CPUs. Develops SystemVerilog testbenches, coverage-driven tests, and CI/CD pipelines for hardware validation.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

RTL engineer at Tenstorrent designing hardware modules for automotive SoC chiplets. Focus on translating system requirements into clean, testable RTL for safety-critical automotive systems.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize LLK infrastructure and lead bring-up of RISC-V-native agentic AI software stacks, including runtime orchestration and distributed execution frameworks. Work at the hardware-software boundary with CPU architects and compiler engineers.

Power Architect at Tenstorrent designing power management and optimization for AI data center chiplets based on RISC-V. Focus on power delivery networks, thermal analysis, and energy efficiency across silicon and systems.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Performance Architect at Tenstorrent modeling and optimizing AI workloads on custom hardware. Role bridges architecture, software, and RTL to guide next-generation AI accelerator design through performance analysis and hardware-software co-design.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Mixed-signal IC layout design engineer at Tenstorrent building high-performance analog IP for advanced FinFET nodes. Translate schematics into manufacturable layouts for PLLs, VCOs, ADCs, and high-speed I/O blocks integrated into SoCs.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

Infrastructure and Platform Engineer at Tenstorrent building Kubernetes-based platforms for workload orchestration on custom AI accelerator hardware. Focus on platform services, APIs, cluster lifecycle management, and supporting large-scale internal and customer environments.

Infrastructure Automation Engineer at Tenstorrent building automation frameworks for large-scale AI infrastructure provisioning and deployment. Focus on Ansible/AWX, Python/Bash scripting, and CI/CD integration across on-prem data centers and accelerator clusters.