Find your next AI-scored role.

Solutions Architect at LangChain designing and deploying production AI infrastructure and multi-agent systems for enterprise customers. Combines infrastructure engineering, agent development, and customer-facing technical leadership.

Staff Machine Learning Engineer at Twilio building data pipelines, ML infrastructure, and real-time intelligence systems for the Trust Intelligence Platform. Focus on orchestration, feature stores, model training/inference, and cloud-native MLOps.

Applied AI Engineer at Anthropic in Tokyo, advising customers on Claude deployment and LLM implementation patterns. Combines technical architecture guidance, evaluation frameworks, and hands-on engineering support across customer product teams.

Senior Software Engineer at Paradigm building Surface.ai, a talent and culture intelligence platform. Full-stack role shipping AI-driven features across frontend, backend, and data pipelines in a small, fast-moving team.

Machine Learning Engineer at Airbnb building agentic AI systems for customer support. Focus on LLM fine-tuning, multi-agent orchestration, RAG, and production ML infrastructure for Chat and Voice AI assistants.

Senior Solutions Engineer at Webflow, an AI-native digital experience platform. Role involves partnering with customers and sales to architect and demonstrate solutions, conduct discovery and technical validation, and influence product direction. Remote-first in US/Canada with 25% travel.

Engineering Manager, Head of Machine Learning at Hightouch, a marketing AI platform. Lead ML efforts across personalization, identity resolution, content generation, and ML infrastructure for data-driven marketing workflows.

Bluespec design engineer at MatX building silicon for GenAI. Develop hardware RTL using Bluespec (a functional language for hardware), focusing on compute, memory, and connectivity subsystems. Haskell proficiency required; prior hardware experience a bonus.

Verification Engineer at Tenstorrent verifying digital IP and SoC logic at chiplet integration level. Build verification infrastructure, testbenches, and test plans for a high-performance RISC-V CPU platform. Requires 10+ years verification experience and advanced degree in EE/CS.

Technical Program Manager at Tenstorrent driving end-to-end execution of next-generation SoCs from architecture through tape-out and post-silicon validation. Requires 10+ years semiconductor experience and strong technical depth in silicon development alongside program management expertise.

Staff Software Engineer at Tenstorrent building cloud infrastructure, SRE, and operational systems for an AI hardware platform. Focus on infrastructure automation, CI/CD, observability, and bare-metal/Kubernetes provisioning.

Staff Technical Program Manager at Tenstorrent managing end-to-end delivery of AI model IP and software stack to customer environments. Bridges compiler, hardware, and runtime teams to ensure performance, correctness, and deployability of AI systems on custom accelerators.

Staff Ethernet Validation Engineer at Tenstorrent building validation infrastructure for high-speed networking IP in AI acceleration hardware. Focus on silicon bring-up, SerDes tuning, and Ethernet MAC/PHY testing across simulation to production.

Staff Physical Design Engineer at Tenstorrent leading EM and IR-drop simulations for high-performance AI chips. Focus on power delivery, signal integrity, and reliability at advanced nodes (7nm and below).

Staff physical design engineer at Tenstorrent implementing high-performance CPU and AI/ML accelerator blocks. Owns synthesis-to-tapeout flow, optimizing performance, power, and area on advanced process nodes.

Staff Engineer leading emulation infrastructure and technical strategy for Tenstorrent's high-performance RISC-V CPUs. Focus on CPU verification, debug workflows, and cross-functional collaboration to enable silicon bring-up and customer systems.

Staff Design for Test STA Engineer at Tenstorrent building DFT methodology and timing sign-off for next-generation AI processors. Owns static timing analysis, scan insertion, and test mode constraints across complex multi-core SoCs.

Staff Analog/Mixed-Signal Design Engineer at Tenstorrent developing die-to-die chiplet PHY IP and PLLs in advanced FinFET processes. Hands-on ownership of design, verification, layout, tape-out, and silicon bring-up for high-performance AI computing platforms.

Sr Staff Engineer at Tenstorrent designing RTL and SoC architectures for AI chips. Focus on microarchitecture, Verilog/VHDL implementation, and performance optimization for compute and memory systems.

Sr. Staff Engineer at Tenstorrent leading post-silicon validation and bring-up of RISC-V-based SoCs. Owns silicon debug, bare-metal testing, and firmware/software integration across CPU cores, memory systems, and high-speed interfaces.

Sr Staff Engineer at Tenstorrent designing CPU system RTL and microarchitecture for a custom RISC-V processor. Combines multiple cores, clusters, and subsystems while optimizing for power, performance, and area in collaboration with validation and physical design teams.

Sr. Staff Engineer at Tenstorrent designing system software for AI-optimized automotive SoCs. Role bridges hardware-software interfaces, translates market requirements into technical specs, and collaborates across hardware, product, and software teams.

Sr Staff Engineer at Tenstorrent developing ASIC design methodologies and infrastructure for RTL development, verification, and physical implementation. Focus on design quality, automation, and enabling scalability across AI SoC flows.

Senior software engineer at Tenstorrent building TT-Forge, an MLIR-based compiler for AI hardware. Focus on compiler optimization, custom dialects, and transformation passes to enable efficient AI model execution across Tenstorrent hardware.

Senior IP Product Engineer at Tenstorrent guiding customers through integration of AI processors, RISC-V CPUs, and chiplet solutions into their SoCs. Bridges cutting-edge semiconductor technology with customer success, managing technical engagements from pre-silicon to post-silicon validation.