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Senior VLSI test and yield enhancement engineer at Cerebras Systems, building wafer-scale AI chips. Analyze ATE data, perform failure analysis, and drive yield improvements using optical and physical inspection techniques.

Senior/Staff engineer at Cerebras Systems bringing up and optimizing the Wafer Scale Engine (WSE) AI chip. Work spans hardware-software codesign, silicon validation, performance optimization, and cross-functional collaboration with chip design and software teams.

Senior Runtime Engineer at Cerebras Systems designing and optimizing distributed runtime software for large-scale AI training and inference on custom wafer-scale hardware. Focus on high-performance data pipelines, multi-node orchestration, and performance optimization across heterogeneous clusters.

Senior ML Systems Engineer at Cerebras building state-of-the-art training platforms on wafer-scale AI chips. Responsible for bringing up large-scale models (LLaMA, Qwen) on Cerebras CSX systems, spanning model architecture, compiler optimization, runtime integration, and performance tuning.

Senior ML Software Engineer at Cerebras Systems integrating and validating the software stack for the Cerebras AI platform. Focus on distributed systems debugging, automation, and reliability across ML infrastructure and hardware/software co-design.

Senior Mechanical Engineer at Cerebras Systems designing mechanical systems for wafer-scale AI chips. Lead design from concept through production, collaborate across teams on electro-mechanical infrastructure for next-generation hardware.

Senior Hardware Technical Program Manager at Cerebras Systems managing end-to-end schedules for AI chip design, manufacturing, and deployment. Owns program planning, risk mitigation, and cross-functional coordination across engineering, supply chain, and software teams.

Principal ML Investigator at Cerebras Systems building ML research and advanced development on the company's wafer-scale AI chip platform. Focus on post-training, dataset optimization, LLM pretraining, sparsity, and domain-specific agents.

Principal Engineer at Cerebras Systems building reliability infrastructure for the world's fastest AI inference service. Owns SLO definition, incident response, and fault-tolerance mechanisms across distributed wafer-scale systems and multi-region cloud deployments.

Principal Engineer at Cerebras Systems building the cloud platform for wafer-scale AI inference. Owns multi-region architecture, reliability, latency optimization, and production operations for high-QPS inference services.

Performance & Reliability Engineer at Cerebras Systems optimizing ML workloads on the company's wafer-scale AI chip. Focus on characterizing hardware/software performance, power efficiency, and thermal management for next-generation AI systems.

ML Systems Performance Engineer at Cerebras Systems optimizing inference speed and throughput on wafer-scale AI chips. Role spans kernel optimization, performance modeling, and debugging across hardware and software layers.

Network Architect at Cerebras Systems designing front-end datacenter and interconnect architecture for AI/ML clusters. Responsible for developing proof-of-concept network designs, resolving performance bottlenecks, and leading cross-functional projects integrating hardware and software components.

ML Software Tool Development Engineer at Cerebras Systems building debugging, validation, and observability platforms for the world's largest AI chip. Focus on system-level profiling, compiler instrumentation, and high-performance hardware-software co-design.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, automation, and process optimization.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, and process automation using Python/Perl scripting.

Lead RTL Design Engineer at Cerebras Systems designing the next-generation Wafer Scale Engine AI chip. Responsibilities include RTL development, synthesis, vendor management, and collaboration with design verification and physical design teams to deliver high-performance semiconductor architectures.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and domain-specific language programming.

Infrastructure Hardware Technical Program Manager at Cerebras Systems driving end-to-end delivery of server and network platforms for AI clusters. Manages OEM/ODM partnerships, qualification, and production rollout across multi-team programs.

Engineering Manager, Kernel Reliability at Cerebras Systems. Lead a team improving reliability of advanced compute clusters and inference/training services. Focus on diagnostic tooling, failure analysis, and kernel-level debugging for wafer-scale AI chip systems.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

Electrical engineer at Cerebras Systems designing printed circuit boards for AI inference chips. Lead PCB development from schematic through production, collaborate with cross-functional teams on power delivery and signal integrity.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Distributed Software Engineer at Cerebras Systems building cluster orchestration and monitoring software for wafer-scale AI supercomputers. Focus on bare-metal automation, Kubernetes-based scheduling, and large-scale distributed systems infrastructure.

Design Validation Test Lead at Cerebras Systems, a hardware AI chip company. Own end-to-end DVT for complex PCBs and systems, including power delivery, high-speed I/O, and thermal validation. Drive debug, root-cause analysis, and design closure.