Find your next AI-scored role.

Software engineer at Tenstorrent designing host and device APIs for Metal runtime on AI accelerators. Focus on low-level systems, performance abstractions, and hardware-software integration.

Software engineer at Tenstorrent building low-level runtime systems for AI accelerators. Focus on scheduling, memory movement, and high-performance execution on custom hardware.

Senior SoC physical design engineer at Tenstorrent building top-level implementations for AI and CPU chips. Responsibilities include floorplanning, power grids, clock networks, and design closure across complex multi-million gate designs.

Software Engineer leading compiler development at Tenstorrent on TT-Forge, an MLIR-based compiler for AI workloads. Focus on graph transformations, lowering passes, kernel optimizations, and team mentorship across hardware and ML integration.

SOC Emulation Engineer at Tenstorrent supporting hardware emulation infrastructure for chip design. Integrates hardware transactors, develops Python test frameworks, and provides technical support to emulation users across multiple projects.

Silicon Power & Characterization Lead at Tenstorrent. Own post-silicon power measurement strategy, build lab infrastructure and automated workflows, and correlate silicon data to pre-silicon models for cutting-edge AI semiconductor products.

RISC-V AI/HPC & Agentic Software Engineering Lead at Tenstorrent. Optimize low-level kernel infrastructure and build agentic AI software stacks on custom RISC-V processors, working at the hardware-software boundary.

RISC-V CPU microarchitecture and RTL design engineer at Tenstorrent. Develop CPU unit specifications, RTL design, and verification for high-performance AI accelerator hardware. Uses AI tools to accelerate design process.

Physical Design Engineer at Tenstorrent performing static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs. Optimize timing paths, debug constraints, and collaborate with logic, DFT, and physical design teams.

Memory Architect at Tenstorrent designing memory chiplet architecture for AI and CPU applications. Responsible for defining memory/I/O specifications, evaluating next-generation memory technologies, and developing performance/power modeling infrastructure.

Senior High Speed Interconnect / Signal Integrity Engineer at Tenstorrent designing and validating high-bandwidth links for large-scale AI systems. Focus on copper and optical interconnect solutions for AI inference and training clusters at speeds up to 1.6T.

Infrastructure and Platform Development Engineer at Tenstorrent building Kubernetes-based platforms for AI workload orchestration and on-prem data center management. Focus on APIs, cluster operations, and infrastructure-as-code automation.

GCC Compiler Engineer at Tenstorrent designing and optimizing compilers for custom RISC-V and AI compute architectures. Focus on hardware-software co-design, performance tuning, and ML framework integration.

Fabric SOC Architect at Tenstorrent designing high-performance interconnect and cache coherency for AI/HPC systems. Role bridges ML software stacks, compilers, and CPU design to optimize SoC performance through data-driven architectural decisions.

Engineering Program Manager at Tenstorrent leading RISC-V CPU development from specification through tapeout and post-silicon debug. Manages cross-functional teams across architecture, design, verification, and physical design to deliver high-performance silicon.

Director of Systems & Solutions at Tenstorrent leading a team to deploy and optimize AI hardware and high-performance compute systems. Hands-on technical leadership combining CPU/GPU architecture expertise with customer-facing systems integration and scaling.

CPU Architect at Tenstorrent designing and optimizing the load-store unit for high-performance RISC-V processors. Focus on micro-architecture, performance modeling, and memory subsystem optimization.

C++ Machine Learning Engineer at Tenstorrent building high-performance training frameworks for AI models on custom silicon. Focus on implementing operators, layers, and optimizing model performance across the company's RISC-V platform.

Automotive and Robotics SoC Architect at Tenstorrent designing scalable system architectures for next-generation automotive AI applications. Requires deep expertise in SoC design, automotive safety standards, and hardware/software co-design.

AI Performance Simulation Architect at Tenstorrent building cycle-accurate performance models for AI accelerators and system-level optimization. Role spans hardware simulation, performance modeling, and architectural design guidance.

Physical Design Engineer at Tenstorrent architecting AI/ML-driven solutions for RTL-to-GDS flows on advanced semiconductor nodes. Focus on PPA optimization, EDA tool integration, and deploying machine learning techniques in production CAD environments.

Staff Software Engineer at Databricks building AI-powered agentic interfaces and generative AI products. Focus on full-stack development combining frontend (React/modern JS) and backend systems for complex workflow management with human oversight.

UX Writer at Figma focused on AI-powered products. Craft language and interaction patterns for AI features, define best practices for prompting and outputs, and partner with designers, engineers, and AI researchers to shape product strategy.

Software Engineer at SambaNova building the SambaStack AI inference serving platform. Focus on performance, scalability, and reliability of enterprise-grade model deployment infrastructure using Python, Go, and Rust.

Principal Engineer at SambaNova leading post-silicon validation of high-speed IO and memory subsystems for the DataScale AI compute platform. Owns bring-up, debug, and deployment of critical hardware interfaces from first silicon through customer deployment.