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Staff Software Engineer building observability platforms at Cerebras Systems, a company making AI inference chips. Focus on designing telemetry pipelines, monitoring infrastructure, and developer tooling for high-scale distributed systems.

Staff Software Engineer at Cerebras Systems building the cloud platform for AI inference. Focus on distributed systems, multi-region architecture, reliability, and latency optimization for high-QPS inference workloads.

Staff Site Reliability Engineer at Cerebras Systems building self-service platforms and automation for AI inference infrastructure. Focus on GitOps-driven CD, observability, and reliability practices for wafer-scale compute clusters serving frontier AI labs.

Staff Python/PyTorch developer at Cerebras Systems building the frontend inference compiler for the world's largest AI chip. Focus on model representation, optimization, and compilation stack for generative AI inference.

Staff LLVM compiler engineer at Cerebras Systems designing and implementing low-level compiler components (backend, assembler, linker) for the company's wafer-scale AI chip architecture. Focus on code generation optimization, LLVM mid-end/backend passes, and single-core performance targeting.

Staff Inference ML Runtime Engineer at Cerebras Systems building high-throughput, low-latency inference serving infrastructure for generative AI models on custom wafer-scale hardware. Focus on ML features, multimodal support, performance optimization, and scalable distributed runtime APIs.

Staff full-stack technical lead at Cerebras Systems building the Developer Console for AI inference workloads. Owns critical platform systems including billing, usage tracking, and observability across frontend (Next.js, TypeScript) and backend (GraphQL, Postgres, Redis).

Staff Compiler Engineer at Cerebras Systems designing and implementing features in CSL, a Zig-like language for programming wafer-scale AI chips. Focus on frontend language design, MLIR/LLVM IR lowering, and compiler optimization for next-generation AI hardware.

Sr. Staff/Principal software security engineer at Cerebras Systems securing large-scale AI inference infrastructure. Design and implement security controls across APIs, control planes, distributed systems, and runtime environments for high-performance ML workloads.

Software engineer at Cerebras Systems building kernel reliability and debugging tools for AI compute clusters. Focus on failure analysis, root-cause investigation, and improving reliability of training and inference systems at scale.

Software Automation Engineer at Cerebras Systems building test automation and infrastructure for AI chip systems. Develops automation frameworks, CI/CD pipelines, and monitoring tools using Python and Linux in a hardware-software integration environment.

Site Reliability Engineer at Cerebras Systems supporting high-performance AI inference infrastructure powered by wafer-scale chips. Focus on Kubernetes operations, automation, observability, and continuous delivery pipelines for production systems serving frontier AI models.

Senior VLSI test and yield enhancement engineer at Cerebras Systems, building wafer-scale AI chips. Analyze ATE data, perform failure analysis, and drive yield improvements using optical and physical inspection techniques.

Senior/Staff engineer at Cerebras Systems bringing up and optimizing the Wafer Scale Engine (WSE) AI chip. Work spans hardware-software codesign, silicon validation, performance optimization, and cross-functional collaboration with chip design and software teams.

Senior Runtime Engineer at Cerebras Systems designing and optimizing distributed runtime software for large-scale AI training and inference on custom wafer-scale hardware. Focus on high-performance data pipelines, multi-node orchestration, and performance optimization across heterogeneous clusters.

Senior ML Systems Engineer at Cerebras building state-of-the-art training platforms on wafer-scale AI chips. Responsible for bringing up large-scale models (LLaMA, Qwen) on Cerebras CSX systems, spanning model architecture, compiler optimization, runtime integration, and performance tuning.

Senior ML Software Engineer at Cerebras Systems integrating and validating the software stack for the Cerebras AI platform. Focus on distributed systems debugging, automation, and reliability across ML infrastructure and hardware/software co-design.

Senior Mechanical Engineer at Cerebras Systems designing mechanical systems for wafer-scale AI chips. Lead design from concept through production, collaborate across teams on electro-mechanical infrastructure for next-generation hardware.

Senior IC Design Engineer at Cerebras Systems focused on signal integrity and power delivery for wafer-scale AI chip architecture. Responsibilities include IO interface design, PDN modeling, and system-level analysis across die, packaging, and board integration.

Senior Hardware Technical Program Manager at Cerebras Systems managing end-to-end schedules for AI chip design, manufacturing, and deployment. Owns program planning, risk mitigation, and cross-functional coordination across engineering, supply chain, and software teams.

Product Manager for Strategic Verticals at Cerebras Systems, a wafer-scale AI chip company. Role involves embedding with strategic customers to translate their AI ambitions into production solutions, design performance benchmarks, and shape product roadmap based on customer insights.

Principal ML Investigator at Cerebras Systems building ML research and advanced development on the company's wafer-scale AI chip platform. Focus on post-training, dataset optimization, LLM pretraining, sparsity, and domain-specific agents.

Principal Engineer at Cerebras Systems building reliability infrastructure for the world's fastest AI inference service. Owns SLO definition, incident response, and fault-tolerance mechanisms across distributed wafer-scale systems and multi-region cloud deployments.

Principal Engineer at Cerebras Systems building the cloud platform for wafer-scale AI inference. Owns multi-region architecture, reliability, latency optimization, and production operations for high-QPS inference services.

Performance & Reliability Engineer at Cerebras Systems optimizing ML workloads on the company's wafer-scale AI chip. Focus on characterizing hardware/software performance, power efficiency, and thermal management for next-generation AI systems.