Find your next AI-scored role.

Manufacturing Test Manager at Cerebras Systems leading test engineering teams for AI chip production. Oversees test strategies, automation systems, and quality assurance for wafer-scale AI processors.

ML Performance Benchmarking Engineer at Cerebras Systems building observability and benchmarking infrastructure for AI inference on wafer-scale hardware. Focus on telemetry systems, performance analysis, and optimization across the full software stack.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, automation, and process optimization.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, and process automation using Python/Perl scripting.

Lead RTL Design Engineer at Cerebras Systems designing the next-generation Wafer Scale Engine AI chip. Responsibilities include RTL development, synthesis, vendor management, and collaboration with design verification and physical design teams to deliver high-performance semiconductor architectures.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and domain-specific language programming.

Infrastructure Hardware Technical Program Manager at Cerebras Systems driving end-to-end delivery of server and network platforms for AI clusters. Manages OEM/ODM partnerships, qualification, and production rollout across multi-team programs.

Inference Frontend engineer at Cerebras Systems building software for the world's largest AI chip. Recent graduate role collaborating on real-world challenges across the software stack, from hardware to ML frameworks.

Engineering Manager, Kernel Reliability at Cerebras Systems. Lead a team improving reliability of advanced compute clusters and inference/training services. Focus on diagnostic tooling, failure analysis, and kernel-level debugging for wafer-scale AI chip systems.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

Electrical engineer at Cerebras Systems designing printed circuit boards for AI inference chips. Lead PCB development from schematic through production, collaborate with cross-functional teams on power delivery and signal integrity.

Early-career compiler engineer at Cerebras Systems building LLVM-based code generation and optimization for the company's wafer-scale AI chip architecture. Focus on low-level compiler components, backend passes, and single-core code generation for massively parallel systems.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Distributed Software Engineer at Cerebras Systems building cluster orchestration and monitoring software for wafer-scale AI supercomputers. Focus on bare-metal automation, Kubernetes-based scheduling, and large-scale distributed systems infrastructure.

Design Validation Test Lead at Cerebras Systems, a hardware AI chip company. Own end-to-end DVT for complex PCBs and systems, including power delivery, high-speed I/O, and thermal validation. Drive debug, root-cause analysis, and design closure.

Design Verification Engineer at Cerebras Systems building verification infrastructure for the world's largest AI chip. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM across simulation, emulation, and silicon bring-up phases.

Compute Server Platform Architect at Cerebras Systems designing x86 server platforms for AI cluster infrastructure. Owns server architecture, performance modeling, and vendor partnerships for Cerebras' wafer-scale AI accelerator systems.

New graduate engineer at Cerebras Systems working on wafer-scale AI chip architecture, kernel design, and performance modeling. Role spans hardware-software codesign, system bringup, and validation across simulators and actual hardware.

Applied Machine Learning Research Scientist at Cerebras Systems building LLM training, fine-tuning, and post-training pipelines on wafer-scale AI hardware. Focus on implementing ML techniques at scale, debugging ML systems, and optimizing training workflows.

AI Silicon Physical Design Engineer at Cerebras Systems building wafer-scale AI chips. Role focuses on synthesizing, placing, routing high-speed designs, and full-chip physical verification for the world's largest AI processor.

Product Manager for AI Models at Cerebras Systems, leading the strategic model portfolio for the world's fastest AI inference platform. Owns model roadmap decisions, quality standards, customer partnerships, and go-to-market launches for frontier and open-source models.

Entry-level AI Infrastructure Operations Engineer at Cerebras Systems supporting deployment, monitoring, and troubleshooting of wafer-scale AI chip infrastructure in data center environments. Focuses on hardware bring-up, telemetry monitoring, and first-line incident response.

AI Infrastructure Operations Engineer at Cerebras Systems managing wafer-scale AI compute clusters. Responsibilities include cluster health monitoring, container deployment, resource optimization, and 24/7 infrastructure support for large-scale ML workloads.

AI/ML Research Scientist at Cerebras Systems designing and developing AI models and training methodologies on wafer-scale hardware. Work spans optimization theory, model architecture, and computational science to explore new algorithmic possibilities enabled by novel hardware architecture.

R&D Engineer at Cerebras Systems designing and optimizing AI/ML and scientific computing workloads on wafer-scale hardware. Work spans algorithm design, compiler co-optimization, and hardware architecture to advance state-of-the-art performance benchmarks.