MatX

Hardware architect at MatX designing silicon for AI models. Responsible for full-chip or subsystem architecture, performance optimization, and cross-team collaboration on vertically integrated hardware-software solutions.

Software engineer at MatX designing and optimizing ML kernels for specialized hardware. Work on vertically integrated compute platform for AGI, interfacing with hardware and ML research teams using Rust, C++, and low-level optimization techniques.

System Software Engineer at MatX building runtime software for custom AI accelerators. Focus on Linux device drivers, kernel optimization, and ML workload scheduling for high-performance GenAI silicon.

ASIC/SOC silicon physical design engineer at MatX building AI accelerator chips. Responsible for RTL-to-GDSII physical design across compute, memory, and connectivity subsystems in leading-edge process nodes.

SOC Architect at MatX designing next-generation AI-focused server-class silicon. Lead architecture from PRDs through productization, defining memory, interconnects, power, and performance trade-offs for AI hardware.

SoC Architect at MatX designing next-generation AI-focused server-class silicon. Lead architecture definition for memory, interconnects, power, and system integration across hardware and software teams.

SOC Micro-architecture and RTL Design Lead at MatX, a silicon company building compute platforms for AGI. Manage a team of micro-architects and RTL designers delivering high-performance chip designs for ML workloads.

Software engineer at MatX designing and implementing compilers for proprietary hardware architecture. Focus on midend and backend development, register allocation, instruction scheduling, and loop optimizations for AGI compute platform.

Security Co-Design Architect at MatX building chip and system security for AI datacenter workloads. Owns end-to-end security architecture across hardware, firmware, and software, including threat modeling, secure boot, key management, and cross-team design reviews.

Software engineer at MatX building hardware simulators and performance models for AGI compute infrastructure. Focus on Rust-based simulator development, hardware architecture modeling, and cross-functional collaboration with architecture and compiler teams.

ASIC/SOC silicon verification engineer at MatX building AI accelerator chips. Responsible for verification methodology, testbenches, and coverage closure across subsystems and full-chip validation for high-performance compute silicon.

Bluespec design engineer at MatX building silicon for GenAI. Develop hardware RTL using Bluespec (a functional language for hardware), focusing on compute, memory, and connectivity subsystems. Haskell proficiency required; prior hardware experience a bonus.

ASIC/SOC Physical Design CAD Engineer at MatX building silicon for AI inference. Develop and maintain RTL-to-GDSII physical design flow, automate backend runs, evaluate EDA tools, and optimize for performance and power on leading-edge process nodes.

Silicon Design-for-Test engineer at MatX building AGI compute hardware. Responsible for DFT implementation, PHY firmware loading, test program development, and silicon bring-up across leading-edge process nodes.

Rust engineer at MatX building silicon verification infrastructure for GenAI chips. Write tests that verify software models and hardware designs match specifications, develop test harnesses, and explore corner cases using randomization.