MatX

Senior/Staff Emulation Engineer at MatX building infrastructure and debug flows for advanced connectivity SoCs. Role spans RTL, software, tooling, and system debug across emulation, simulation, and post-silicon validation for AGI compute platforms.

Hardware architect at MatX designing silicon for AI models. Responsible for full-chip or subsystem architecture, performance optimization, and cross-team collaboration on vertically integrated hardware-software solutions.

AI Accelerator Silicon Architect at MatX designing compute subsystems for next-generation GenAI accelerators. Define ISA, connectivity, memory architecture, and conduct performance analysis for high-performance AI hardware.

Runtime Engineer at MatX building the host-side stack for custom silicon inference and training accelerators. Owns device memory management, Python bindings, LLM serving infrastructure, and hardware-software contracts across compiler, runtime, and kernel layers.

Software engineer at MatX designing and optimizing ML kernels for AGI compute infrastructure. Work on hardware-software integration using Rust, C++, and low-level optimization techniques for specialized hardware.

Software engineer at MatX designing and implementing compilers for proprietary hardware architecture. Focus on midend and backend development, register allocation, instruction scheduling, and loop optimizations for AGI compute platform.

SOC Integration Engineer at MatX designing full-chip RTL for AGI compute hardware. Responsible for integrating subsystems, managing clock/reset methodologies, and automating SOC top-level design flows using SystemVerilog and Python.

SOC Architect at MatX designing next-generation AI-focused server-class silicon. Lead architecture translation from PRDs to SoC-level designs, define memory/interconnect/power systems, and drive PPA trade-offs across hardware and software teams.

SOC Architect at MatX designing next-generation AI-focused server-class silicon. Lead SoC architecture from PRDs through productization, defining memory, interconnects, power, and performance trade-offs for AI hardware acceleration.

ASIC/SOC silicon physical design engineer at MatX building AI accelerator chips. Responsible for RTL-to-GDSII physical design, floorplanning, place & route, and sign-off across compute and memory subsystems in leading-edge process nodes.

Silicon micro-architect and RTL designer at MatX building vertically integrated hardware and software for AGI compute. Responsible for subsystem and chip-level silicon design from architecture through sign-off, focusing on high-performance compute, memory, and connectivity.

Build Systems Engineer at MatX, a custom AI accelerator silicon company. Owns Bazel build graph, toolchains, EDA tool integrations, and CI infrastructure. Focus on hermeticity, performance, and build system design.

Software engineer at MatX building hardware simulators and performance models for AGI compute infrastructure. Focus on Rust-based tools for ML accelerator validation, debugging, and optimization.

Formal Verification Engineer at MatX building AI hardware and compiler infrastructure. Apply model checking, theorem proving, and formal methods to verify RTL, memory systems, and compiler correctness across the full stack.

System Software Engineer at MatX building silicon for high-performance GenAI. Focus on Linux device drivers, kernel optimization, system software architecture, and hardware bring-up for custom accelerators.

ASIC/SOC silicon verification engineer at MatX building custom AI accelerator silicon. Responsible for verification methodology, testbenches, and coverage closure across subsystems and full-chip validation for high-performance compute and memory systems.

ASIC/SOC Physical Design CAD Engineer at MatX building silicon for GenAI. Develop and maintain RTL-to-GDSII physical design flow, automate backend runs, evaluate EDA tools, and support design teams on leading-edge process nodes.

Hardware Systems Electrical Engineer at MatX designing compute boards and interconnects for AI data center platforms. Responsible for board design, schematic capture, verification, and lab bring-up for rack-scale AI infrastructure.

Hardware System Diagnostic Engineer at MatX building diagnostics test suites for AI accelerator boards and rack-scale data center products. Owns end-to-end testing for manufacturing, debugging, and deployment of custom silicon systems.

Silicon Design-for-Test engineer at MatX building AGI compute hardware. Responsible for DFT implementation, PHY firmware loading, test program development, and silicon bring-up across leading-edge process nodes.

Bluespec Design Engineer at MatX building silicon for GenAI. Design production hardware RTL using Bluespec (a functional hardware description language), develop reusable libraries, and shape chip architecture. Requires strong Haskell proficiency; prior hardware experience not required.

Rust engineer at MatX building silicon verification infrastructure for GenAI chips. Write Rust tests that verify software models and hardware designs match specifications, develop test harnesses, and catch silicon bugs before fabrication.

Mechanical and thermal reliability engineer at MatX developing rack and POD-level infrastructure for AI/HPC workloads. Focus on reliability testing, qualification, and thermal management for liquid cooling systems and compute hardware.

Infrastructure engineer at MatX, a custom chip design company. Focus on Linux, networking, CI/CD, and internal tooling to support a compute-heavy engineering environment. Hybrid role based in Mountain View, CA.

Executive Operations Coordinator at MatX supporting the CEO and Chief of Staff. Manages calendaring, communications, meeting logistics, and cross-functional project execution for an AI infrastructure company.