Cerebras Systems

Principal ML Investigator at Cerebras Systems building ML research and advanced development on the company's wafer-scale AI chip platform. Focus on post-training, dataset optimization, LLM pretraining, sparsity, and domain-specific agents.

AI/ML Research Scientist at Cerebras Systems designing and developing AI models and training methodologies on wafer-scale hardware. Work spans optimization theory, model architecture, and computational science to explore new algorithmic possibilities enabled by novel hardware architecture.

Applied AI/ML Scientist at Cerebras Systems developing and customizing large language models on the company's wafer-scale AI chip. Responsibilities include training custom models, fine-tuning LLMs, designing agentic systems, and serving as technical expert for customer AI initiatives.

LLM Inference Performance & Evals Engineer at Cerebras Systems building performance-eval pipelines and benchmarking cutting-edge model optimizations on wafer-scale hardware. Prototype architectural tweaks, develop agent-driven automation for experiments, and collaborate across compiler, runtime, and silicon teams.

R&D Engineer at Cerebras Systems designing and optimizing AI/ML and scientific computing workloads on wafer-scale hardware. Work spans algorithm design, compiler co-optimization, and hardware architecture to advance state-of-the-art performance benchmarks.

Applied Machine Learning Research Scientist at Cerebras Systems building LLM training, fine-tuning, and post-training pipelines on wafer-scale AI hardware. Focus on implementing ML techniques at scale, debugging ML systems, and optimizing training workflows.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

ML Research Engineer at Cerebras Systems optimizing transformer models for inference on the company's wafer-scale AI chip. Focus on speculative decoding, pruning, compression, and sparse attention techniques to deliver low-latency inference at scale.

Compiler engineer at Cerebras Systems building the Tungsten dataflow compiler for wafer-scale AI processors. Design and implement compiler passes, optimize code generation for novel hardware, and co-design language constructs for efficient execution across hundreds of thousands of cores.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and custom domain-specific language programming.

ML Systems Performance Engineer at Cerebras Systems optimizing inference speed and throughput on wafer-scale AI chips. Role spans kernel optimization, performance modeling, and debugging across hardware and software layers.

Senior/Staff engineer at Cerebras Systems bringing up and optimizing the Wafer Scale Engine (WSE) AI chip. Work spans hardware-software codesign, silicon validation, performance optimization, and cross-functional collaboration with chip design and software teams.

Senior/Staff engineer at Cerebras Systems bringing up and optimizing the Wafer Scale Engine (WSE) AI chip. Work spans hardware-software codesign, silicon validation, performance optimization, and cross-functional collaboration with chip design and software teams.

Full Stack LLM Engineer at Cerebras Systems bringing up state-of-the-art models on wafer-scale AI chips. Work spans model architecture, compiler optimization, runtime integration, and performance tuning across the entire software stack.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and domain-specific language programming.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations, implementing parallel algorithms, and leveraging custom hardware architecture.

Senior ML Systems Engineer at Cerebras building state-of-the-art training platforms on wafer-scale AI chips. Responsible for bringing up large-scale models (LLaMA, Qwen) on Cerebras CSX systems, spanning model architecture, compiler optimization, runtime integration, and performance tuning.

Staff Compiler Engineer at Cerebras Systems designing and implementing features in CSL, a Zig-like language for programming wafer-scale AI chips. Focus on frontend language design, MLIR/LLVM IR lowering, and compiler optimization for next-generation AI hardware.

Staff Inference ML Runtime Engineer at Cerebras Systems building high-throughput, low-latency inference serving infrastructure for generative AI models on custom wafer-scale hardware. Focus on ML features, multimodal support, performance optimization, and scalable distributed runtime APIs.

Staff Python/PyTorch developer at Cerebras Systems building the frontend inference compiler for the world's largest AI chip. Focus on model representation, optimization, and compilation stack for generative AI inference.

Senior Performance Engineer at Cerebras Systems building benchmarking and competitive intelligence for AI inference performance. Focuses on reproducible benchmarks, GPU optimization, and pricing analysis across inference providers.

QA Lead at Cerebras Systems ensuring quality of ML software across training and inference workloads. Responsibilities include testing ML models, automating test workflows, debugging large-scale deployments, and validating customer workloads on Cerebras' wafer-scale AI chip platform.

Product Manager for Strategic Verticals at Cerebras Systems, a wafer-scale AI chip company. Role involves embedding with strategic customers to translate their AI ambitions into production solutions, design performance benchmarks, and shape product roadmap based on customer insights.

Staff LLVM compiler engineer at Cerebras Systems designing and implementing low-level compiler components (backend, assembler, linker) for the company's wafer-scale AI chip architecture. Focus on code generation optimization, LLVM mid-end/backend passes, and single-core performance targeting.

Early-career compiler engineer at Cerebras Systems building LLVM-based code generation and optimization for the company's wafer-scale AI chip architecture. Focus on low-level compiler components, backend passes, and single-core code generation for massively parallel systems.

Senior Runtime Engineer at Cerebras Systems designing and optimizing distributed runtime software for large-scale AI training and inference on custom wafer-scale hardware. Focus on high-performance data pipelines, multi-node orchestration, and performance optimization across heterogeneous clusters.

Lead RTL Design Engineer at Cerebras Systems designing the next-generation Wafer Scale Engine AI chip. Responsibilities include RTL development, synthesis, vendor management, and collaboration with design verification and physical design teams to deliver high-performance semiconductor architectures.

Compute Server Platform Architect at Cerebras Systems designing x86 server platforms for AI cluster infrastructure. Owns server architecture, performance modeling, and vendor partnerships for Cerebras' wafer-scale AI accelerator systems.

ML Software Tool Development Engineer at Cerebras Systems building debugging, validation, and observability platforms for the world's largest AI chip. Focus on system-level profiling, compiler instrumentation, and high-performance hardware-software co-design.

Principal Engineer at Cerebras Systems building the cloud platform for wafer-scale AI inference. Owns multi-region architecture, reliability, latency optimization, and production operations for high-QPS inference services.

Principal Engineer at Cerebras Systems building reliability infrastructure for the world's fastest AI inference service. Owns SLO definition, incident response, and fault-tolerance mechanisms across distributed wafer-scale systems and multi-region cloud deployments.

3D physical design engineer at Cerebras Systems building wafer-scale AI chip architecture. Focus on ASIC/SoC design, 3D packaging, power/thermal analysis, and physical verification for next-generation AI inference hardware.

Product Manager for AI Models at Cerebras Systems, leading the strategic model portfolio for the world's fastest AI inference platform. Owns model roadmap decisions, quality standards, customer partnerships, and go-to-market launches for frontier and open-source models.

AI Silicon Physical Design Engineer at Cerebras Systems building wafer-scale AI chips. Role focuses on synthesizing, placing, routing high-speed designs, and full-chip physical verification for the world's largest AI processor.

Inference Frontend engineer at Cerebras Systems building software for the world's largest AI chip. Recent graduate role collaborating on real-world challenges across the software stack, from hardware to ML frameworks.

New graduate engineer at Cerebras Systems working on wafer-scale AI chip architecture, kernel design, and performance modeling. Role spans hardware-software codesign, system bringup, and validation across simulators and actual hardware.

Design Verification Engineer at Cerebras Systems building verification infrastructure for the world's largest AI chip. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM across simulation, emulation, and silicon bring-up phases.

Infrastructure Hardware Technical Program Manager at Cerebras Systems driving end-to-end delivery of server and network platforms for AI clusters. Manages OEM/ODM partnerships, qualification, and production rollout across multi-team programs.

Senior ML Software Engineer at Cerebras Systems integrating and validating the software stack for the Cerebras AI platform. Focus on distributed systems debugging, automation, and reliability across ML infrastructure and hardware/software co-design.

Staff Software Engineer at Cerebras Systems building the cloud platform for AI inference. Focus on distributed systems, multi-region architecture, reliability, and latency optimization for high-QPS inference workloads.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Engineering Manager, Kernel Reliability at Cerebras Systems. Lead a team improving reliability of advanced compute clusters and inference/training services. Focus on diagnostic tooling, failure analysis, and kernel-level debugging for wafer-scale AI chip systems.

ML Performance Benchmarking Engineer at Cerebras Systems building observability and benchmarking infrastructure for AI inference on wafer-scale hardware. Focus on telemetry systems, performance analysis, and optimization across the full software stack.

Manufacturing Test Manager at Cerebras Systems leading test engineering teams for AI chip production. Oversees test strategies, automation systems, and quality assurance for wafer-scale AI processors.

Network Architect at Cerebras Systems designing front-end datacenter and interconnect architecture for AI/ML clusters. Responsible for developing proof-of-concept network designs, resolving performance bottlenecks, and leading cross-functional projects integrating hardware and software components.

Performance Engineer at Cerebras Systems optimizing CPU and memory subsystems for the CS-3 AI accelerator runtime. Focus on x86 architecture tuning, algorithm optimization, and profiling to enable faster ML training and inference workloads.

Performance & Reliability Engineer at Cerebras Systems optimizing ML workloads on the company's wafer-scale AI chip. Focus on characterizing hardware/software performance, power efficiency, and thermal management for next-generation AI systems.

Sr. Staff/Principal software security engineer at Cerebras Systems securing large-scale AI inference infrastructure. Design and implement security controls across APIs, control planes, distributed systems, and runtime environments for high-performance ML workloads.

AI Infrastructure Operations Engineer at Cerebras Systems managing wafer-scale AI compute clusters. Responsibilities include cluster health monitoring, container deployment, resource optimization, and 24/7 infrastructure support for large-scale ML workloads.

Staff Site Reliability Engineer at Cerebras Systems building self-service platforms and automation for AI inference infrastructure. Focus on GitOps-driven CD, observability, and reliability practices for wafer-scale compute clusters serving frontier AI labs.

Advanced Packaging Technologist & Lead at Cerebras Systems designing semiconductor packaging technologies for AI chips. Responsibilities include 2.5D/3D stacking, heterogeneous integration, and high-density interconnect architectures for wafer-scale AI compute platforms.

System Software Engineer at Cerebras building embedded and platform software for the Wafer Scale Engine AI processor. Focus on microcontroller firmware, Linux BSP, system monitoring, and cluster orchestration integration.

Distributed Software Engineer at Cerebras Systems building cluster orchestration and monitoring software for wafer-scale AI supercomputers. Focus on bare-metal automation, Kubernetes-based scheduling, and large-scale distributed systems infrastructure.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, and process automation using Python/Perl scripting.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, automation, and process optimization.

Senior IC Design Engineer at Cerebras Systems focused on signal integrity and power delivery for wafer-scale AI chip architecture. Responsibilities include IO interface design, PDN modeling, and system-level analysis across die, packaging, and board integration.

Software engineer at Cerebras Systems building kernel reliability and debugging tools for AI compute clusters. Focus on failure analysis, root-cause investigation, and improving reliability of training and inference systems at scale.

Electrical engineer at Cerebras Systems designing printed circuit boards for AI inference chips. Lead PCB development from schematic through production, collaborate with cross-functional teams on power delivery and signal integrity.

Staff full-stack technical lead at Cerebras Systems building the Developer Console for AI inference workloads. Owns critical platform systems including billing, usage tracking, and observability across frontend (Next.js, TypeScript) and backend (GraphQL, Postgres, Redis).

Senior Hardware Technical Program Manager at Cerebras Systems managing end-to-end schedules for AI chip design, manufacturing, and deployment. Owns program planning, risk mitigation, and cross-functional coordination across engineering, supply chain, and software teams.

Staff Software Engineer building observability platforms at Cerebras Systems, a company making AI inference chips. Focus on designing telemetry pipelines, monitoring infrastructure, and developer tooling for high-scale distributed systems.

Signal Integrity & Power Integrity Engineer at Cerebras Systems designing high-speed interfaces and power delivery networks for AI compute chips. Requires 10+ years expertise in SI/PI analysis, PCB/flex circuit design, and electromagnetic simulation for next-generation hardware systems.

Design Validation Test Lead at Cerebras Systems, a hardware AI chip company. Own end-to-end DVT for complex PCBs and systems, including power delivery, high-speed I/O, and thermal validation. Drive debug, root-cause analysis, and design closure.

Senior Mechanical Engineer at Cerebras Systems designing mechanical systems for wafer-scale AI chips. Lead design from concept through production, collaborate across teams on electro-mechanical infrastructure for next-generation hardware.

Senior VLSI test and yield enhancement engineer at Cerebras Systems, building wafer-scale AI chips. Analyze ATE data, perform failure analysis, and drive yield improvements using optical and physical inspection techniques.

Entry-level AI Infrastructure Operations Engineer at Cerebras Systems supporting deployment, monitoring, and troubleshooting of wafer-scale AI chip infrastructure in data center environments. Focuses on hardware bring-up, telemetry monitoring, and first-line incident response.

Site Reliability Engineer at Cerebras Systems supporting high-performance AI inference infrastructure powered by wafer-scale chips. Focus on Kubernetes operations, automation, observability, and continuous delivery pipelines for production systems serving frontier AI models.

Software Automation Engineer at Cerebras Systems building test automation and infrastructure for AI chip systems. Develops automation frameworks, CI/CD pipelines, and monitoring tools using Python and Linux in a hardware-software integration environment.

Software Development Engineer in Test at Cerebras Systems designing and maintaining automated test frameworks for AI chip systems. Focus on test automation, systems verification, and quality assurance for wafer-scale AI hardware.