AI jobs in Sunnyvale

Senior front-end design engineer at Cerebras Systems building the world's largest AI chip. Focus on RTL design, microarchitecture, and chip integration for wafer-scale AI compute systems.

Design Verification Engineer at Cerebras Systems building verification infrastructure for wafer-scale AI chips. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM to ensure silicon quality across simulation, emulation, and bring-up phases.

Sr. Staff/Staff Design Verification Engineer at Cerebras Systems building verification infrastructure for wafer-scale AI chips. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM to ensure high-quality silicon designs.

ASIC Architect at Cerebras Systems designing wafer-scale AI chip architecture. Translate high-level specs to micro-architecture, perform PPA trade-offs, profile workloads, and optimize for ML inference performance.

Network Architect at Cerebras Systems designing and operating datacenter interconnect fabrics for AI/ML clusters. Role spans hardware-software integration, network reliability, and large-scale distributed systems debugging.

Mechanical Engineer at Cerebras Systems designing mechanical systems for wafer-scale AI chips. Lead design from concept through production, collaborate across teams, and solve complex electro-mechanical challenges in a fast-paced environment.

Design Verification Engineer at Cerebras Systems building verification infrastructure for wafer-scale AI chips. Develops testbenches, test strategies, and coverage plans using SystemVerilog and UVM to ensure silicon quality across simulation, emulation, and bring-up phases.

AI Engineer at Cerebras Systems building model quality and performance systems for wafer-scale AI inference. Design eval suites with AI agents, automate release qualification, and build benchmarking workflows for customer use cases.

Member of Technical Staff (Software Engineer) at Cerebras Systems building high-performance, low-latency inference infrastructure. Focus on Kubernetes orchestration, Python APIs, and deployment optimization for AI inference workloads.

Sr. Technical Staff at Cerebras Systems performing post-silicon validation, hardware bring-up, and debug of wafer-scale AI chips. Develops test automation scripts in Python/bash and collaborates with hardware and software teams on silicon characterization and system integration.

Sr. Member of Technical Staff at Cerebras Systems building inference software and deployment infrastructure for AI chips. Focus on cloud-based workflows, containerization, monitoring, and system reliability using AWS, Kubernetes, and Python.

3D physical design engineer at Cerebras Systems building wafer-scale AI chip architecture. Focus on 3D integration, physical verification, power/performance optimization, and packaging design for the world's largest AI processor.

Prognostics & Health Monitoring Engineer at Cerebras Systems building frameworks to monitor, assess, and predict hardware health across AI chip infrastructure. Role spans reliability engineering, data science, and system software to enable early failure detection and proactive mitigation.

Staff Backend Engineer at Crusoe building high-throughput streaming infrastructure for observability data across AI cloud. Focus on Kafka/Kinesis platforms, reliability at scale, and cross-team technical leadership.

Senior Performance Engineer at Cerebras Systems building benchmarking and competitive intelligence for AI inference performance. Focuses on reproducible benchmarks, GPU optimization, and pricing analysis across inference providers.

Senior Technical Program Manager at Cerebras Systems overseeing site and data center operations for AI infrastructure deployments. Owns end-to-end programs for hardware systems, cloud infrastructure, and operational readiness across cross-functional teams.

System Software Engineer at Cerebras building embedded and platform software for the Wafer Scale Engine AI processor. Focus on microcontroller firmware, Linux BSP, system monitoring, and cluster orchestration integration.

Staff Software Engineer at Cerebras Systems building the cloud platform for AI inference. Focus on distributed systems, multi-region architecture, reliability, and latency optimization for high-QPS inference workloads.

Staff Site Reliability Engineer at Cerebras Systems building self-service platforms and automation for AI inference infrastructure. Focus on GitOps-driven CD, observability, and reliability practices for wafer-scale compute clusters serving frontier AI labs.

Staff Inference ML Runtime Engineer at Cerebras Systems building high-throughput, low-latency inference serving infrastructure for generative AI models on custom wafer-scale hardware. Focus on ML features, multimodal support, performance optimization, and scalable distributed runtime APIs.

Software engineer at Cerebras Systems building kernel reliability and debugging tools for AI compute clusters. Focus on failure analysis, root-cause investigation, and improving reliability of training and inference systems at scale.

Site Reliability Engineer at Cerebras Systems supporting high-performance AI inference infrastructure powered by wafer-scale chips. Focus on Kubernetes operations, automation, observability, and continuous delivery pipelines for production systems serving frontier AI models.

Senior VLSI test and yield enhancement engineer at Cerebras Systems, building wafer-scale AI chips. Analyze ATE data, perform failure analysis, and drive yield improvements using optical and physical inspection techniques.

Senior/Staff engineer at Cerebras Systems bringing up and optimizing the Wafer Scale Engine (WSE) AI chip. Work spans hardware-software codesign, silicon validation, performance optimization, and cross-functional collaboration with chip design and software teams.

Senior Runtime Engineer at Cerebras Systems designing and optimizing distributed runtime software for large-scale AI training and inference on custom wafer-scale hardware. Focus on high-performance data pipelines, multi-node orchestration, and performance optimization across heterogeneous clusters.

Senior ML Systems Engineer at Cerebras building state-of-the-art training platforms on wafer-scale AI chips. Responsible for bringing up large-scale models (LLaMA, Qwen) on Cerebras CSX systems, spanning model architecture, compiler optimization, runtime integration, and performance tuning.

Senior ML Software Engineer at Cerebras Systems integrating and validating the software stack for the Cerebras AI platform. Focus on distributed systems debugging, automation, and reliability across ML infrastructure and hardware/software co-design.

Senior Mechanical Engineer at Cerebras Systems designing mechanical systems for wafer-scale AI chips. Lead design from concept through production, collaborate across teams on electro-mechanical infrastructure for next-generation hardware.

Senior Hardware Technical Program Manager at Cerebras Systems managing end-to-end schedules for AI chip design, manufacturing, and deployment. Owns program planning, risk mitigation, and cross-functional coordination across engineering, supply chain, and software teams.

Principal ML Investigator at Cerebras Systems building ML research and advanced development on the company's wafer-scale AI chip platform. Focus on post-training, dataset optimization, LLM pretraining, sparsity, and domain-specific agents.

Principal Engineer at Cerebras Systems building reliability infrastructure for the world's fastest AI inference service. Owns SLO definition, incident response, and fault-tolerance mechanisms across distributed wafer-scale systems and multi-region cloud deployments.

Principal Engineer at Cerebras Systems building the cloud platform for wafer-scale AI inference. Owns multi-region architecture, reliability, latency optimization, and production operations for high-QPS inference services.

Performance & Reliability Engineer at Cerebras Systems optimizing ML workloads on the company's wafer-scale AI chip. Focus on characterizing hardware/software performance, power efficiency, and thermal management for next-generation AI systems.

ML Systems Performance Engineer at Cerebras Systems optimizing inference speed and throughput on wafer-scale AI chips. Role spans kernel optimization, performance modeling, and debugging across hardware and software layers.

Network Architect at Cerebras Systems designing front-end datacenter and interconnect architecture for AI/ML clusters. Responsible for developing proof-of-concept network designs, resolving performance bottlenecks, and leading cross-functional projects integrating hardware and software components.

ML Software Tool Development Engineer at Cerebras Systems building debugging, validation, and observability platforms for the world's largest AI chip. Focus on system-level profiling, compiler instrumentation, and high-performance hardware-software co-design.

Manufacturing Bring-up Engineer at Cerebras Systems supporting system-level validation and testing of AI chips in the manufacturing pipeline. Responsibilities include hardware bring-up, cross-functional collaboration, and process automation using Python/Perl scripting.

Lead RTL Design Engineer at Cerebras Systems designing the next-generation Wafer Scale Engine AI chip. Responsibilities include RTL development, synthesis, vendor management, and collaboration with design verification and physical design teams to deliver high-performance semiconductor architectures.

Kernel Engineer at Cerebras Systems developing high-performance ML and HPC kernels for the company's wafer-scale AI processor. Focus on optimizing deep learning operations through low-level assembly and domain-specific language programming.

Infrastructure Hardware Technical Program Manager at Cerebras Systems driving end-to-end delivery of server and network platforms for AI clusters. Manages OEM/ODM partnerships, qualification, and production rollout across multi-team programs.

Engineering Manager, Kernel Reliability at Cerebras Systems. Lead a team improving reliability of advanced compute clusters and inference/training services. Focus on diagnostic tooling, failure analysis, and kernel-level debugging for wafer-scale AI chip systems.

Engineering Manager leading Cerebras' ML inference runtime team. Responsible for designing and scaling high-performance inference systems for generative AI models on Cerebras' wafer-scale hardware, managing engineers, and driving cross-functional execution.

Electrical engineer at Cerebras Systems designing printed circuit boards for AI inference chips. Lead PCB development from schematic through production, collaborate with cross-functional teams on power delivery and signal integrity.

Engineering Lead for cluster security at Cerebras Systems, building security solutions for large-scale AI chip clusters. Responsible for end-to-end security architecture, multi-tenancy, and leading a security engineering team across hardware and software layers.

Design Validation Test Lead at Cerebras Systems, a hardware AI chip company. Own end-to-end DVT for complex PCBs and systems, including power delivery, high-speed I/O, and thermal validation. Drive debug, root-cause analysis, and design closure.

Compute Server Platform Architect at Cerebras Systems designing x86 server platforms for AI cluster infrastructure. Owns server architecture, performance modeling, and vendor partnerships for Cerebras' wafer-scale AI accelerator systems.

New graduate engineer at Cerebras Systems working on wafer-scale AI chip architecture, kernel design, and performance modeling. Role spans hardware-software codesign, system bringup, and validation across simulators and actual hardware.

Applied Machine Learning Research Scientist at Cerebras Systems building LLM training, fine-tuning, and post-training pipelines on wafer-scale AI hardware. Focus on implementing ML techniques at scale, debugging ML systems, and optimizing training workflows.

AI Silicon Physical Design Engineer at Cerebras Systems building wafer-scale AI chips. Role focuses on synthesizing, placing, routing high-speed designs, and full-chip physical verification for the world's largest AI processor.

Product Manager for AI Models at Cerebras Systems, leading the strategic model portfolio for the world's fastest AI inference platform. Owns model roadmap decisions, quality standards, customer partnerships, and go-to-market launches for frontier and open-source models.

Entry-level AI Infrastructure Operations Engineer at Cerebras Systems supporting deployment, monitoring, and troubleshooting of wafer-scale AI chip infrastructure in data center environments. Focuses on hardware bring-up, telemetry monitoring, and first-line incident response.

AI Infrastructure Operations Engineer at Cerebras Systems managing wafer-scale AI compute clusters. Responsibilities include cluster health monitoring, container deployment, resource optimization, and 24/7 infrastructure support for large-scale ML workloads.

AI/ML Research Scientist at Cerebras Systems designing and developing AI models and training methodologies on wafer-scale hardware. Work spans optimization theory, model architecture, and computational science to explore new algorithmic possibilities enabled by novel hardware architecture.

R&D Engineer at Cerebras Systems designing and optimizing AI/ML and scientific computing workloads on wafer-scale hardware. Work spans algorithm design, compiler co-optimization, and hardware architecture to advance state-of-the-art performance benchmarks.

Compiler engineer at Cerebras Systems building the Tungsten dataflow compiler for wafer-scale AI processors. Design and implement compiler passes, optimize code generation for novel hardware, and co-design language constructs for efficient execution across hundreds of thousands of cores.

Senior Data Engineer at Crusoe Energy building foundational data platform infrastructure for AI infrastructure operations. Design scalable data systems, ETL pipelines, and data warehouses serving analytics and ML workloads.